> sure, it's as easy as adding the right ranges to the wiki. > can you tell me the end addresses? > > i'm guessing: > > 0x9a00-0x9aff ??? AR5K_RF_GAIN > 0x9b00-0x9c00 ??? AR5K_BB_GAIN ???
RF_GAIN and BB_GAIN tables are 64bytes each so its from AR5K_RF_GAIN(0) to AR5K_RF_GAIN(63) (0x9a00 - 0x9afc) and for BB_GAIN (0x9b00 - 0x9bfc) > 0xa180-0x0a200 ??? AR5K_PHY_PCDAC_TXPOWER ??? this one is 32bytes so it's (0xa180 - 0xa1fc) > 0x8700-0x8800 ??? AR5K_RATE_DUR ??? also 32bytes so it's (0x8700 - 0x877c) > 0x9800- ??? AR5K_PHY > This is indeed weird, it seems that any register from 9800+ is PHY register so we want to display AR5K_PHY for them (those we don't know about). > please confirm... > > another note: > AR5K_KEYTABLE(index) is not handled right, it is treated like the other ranges > with (index << 2). > > bruno > We can skip that for the moment (it should be base + (index << 5)), wep is confirmed to work for now, we need first to fix that b/g cards bug and then phy initialization for 5424/2424 and rest single-chips. -- GPG ID: 0xD21DB2DB As you read this post global entropy rises. Have Fun ;-) Nick _______________________________________________ ath5k-devel mailing list ath5k-devel@lists.ath5k.org https://lists.ath5k.org/mailman/listinfo/ath5k-devel
