John Stimson Wrote: 
> What is the mechanism for upstream jitter to affect the DAC, when the
> master clock for the system is located at the DAC, on its own power
> supply?

I'm not an expert, but the jittery data signal has to pass the 'master
clock gate' at the DAC. What comes out of the gate is jittery/noisy
again.
I guess it's difficult to put high frequency signals together in one
chip, without interacting on each other.


-- 
void
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