Can I inject a wee bit of real information here? Most of the DAC's that claim to eliminate input jitter do so for a very good reason - they use a chip which actually pretty much does that (AD1896). Now, what they don't tell you is that the chip costs ~$17.00 and is really very easy to implement, but hey, that's marketing. Anyway, the DAC I built for myself uses this chip, so I think I'm qualified to talk about it, although I don't have the equipment necessary to do the jitter measurements myself. If you read the data sheet for AD1896, it is very clear that jitter rejection is very good. The tradeoff is that you have to live with your signal being upsampled and decimated, but this is done so accurately, that it did not concern me. Here's some text from the data sheet, and I urge anyone who really is curious about this subject and wants to learn more to Google "AD1896" and download the pdf from the ADI website:
> Conceptually, the AD1896 interpolates the serial input data by a rate of > 220 and samples the interpolated data stream by the output sample rate. > In practice, a 64-tap FIR filter with 220 polyphases, a FIFO, a digital > servo loop that measures the time difference between the input and > output samples within 5 ps, and a digital circuit to track the sample > rate ratio are used to perform the interpolation and output sampling. > Refer to the Theory of Operation section. The digital servo loop and > sample rate ratio circuit automatically track the input and output > sample rates. > > The digital servo loop measures the time difference between the input > and output sample rates within 5 ps. This is necessary in order to > select the correct polyphase filter coefficient. The digital servo loop > has excellent jitter rejection for both input and output sample rates as > well as the master clock. The jitter rejection begins at less than 1 Hz. > This requires a long settling > time whenever RESET is deasserted or when the input or output sample > rate changes. To reduce the settling time, upon deassertion of RESET or > a change in a sample rate, the digital > servo loop enters the fast settling mode. When the digital servo > loop has adequately settled in the fast mode, it switches into the > normal or slow settling mode and continues to settle until the time > difference measurement between input and output sample rates is within > 5 ps. During fast mode, the MUTE_OUT signal is asserted high. Normally, > the MUTE_OUT is connected to the MUTE_IN pin. The MUTE_IN signal is used > to softly mute the AD1896 upon assertion and softly unmute the AD1896 > when it is deasserted. -- ezkcdude DIY projects page: http://www.ezdiyaudio.com System: SB3->EZDAC->MIT Terminator 2 interconnects->Endler Audio 24-step Attenuators (RCA-direct)->Parasound Halo A23 125W/ch amplifier->Speltz anti-cables->DIY 2-ways + Dayton Titanic 10" subwoofer He's not hi-fi, he's my stereo. ------------------------------------------------------------------------ ezkcdude's Profile: http://forums.slimdevices.com/member.php?userid=2545 View this thread: http://forums.slimdevices.com/showthread.php?t=29450 _______________________________________________ audiophiles mailing list audiophiles@lists.slimdevices.com http://lists.slimdevices.com/lists/listinfo/audiophiles
