So how did it work? Do you have the SB playing off the external clock? BTW I want to clear up some terminology here, there seems to be some misunderstanding between "word clock" and MCLK or sysclk. A word clock is a clock with a frequency equal to the sample rate (a "word" in this case is all the bits, both left and right channels for one sample), in this case 44.1 KHz. MCLK (or master clock) is 256 times the word clock or 11.2896 MHz. The "bit clock" is 1/4 of the MCLK.
This technique of feeding a clock into a pad where the crystal used to be HAS to be MCLK NOT a word clock. So if you have a DAC that outputs a clock it has to be a MCLK not a word clock. OR you have to do what Sean mentioned and use a PLL to multiply the word clock 256X to make a MCLK. As far as the jitter goes inside the SB itself the clock multiplication would almost certainly produce more jitter than is already there with the existing crystal, BUT it would allow you to sync the SB to the clock inside the DAC. As long as the DAC is synchronously reclocking the incoming data with its own internal low jitter MCLK this might actually be a usable solution. This scenario would only come into play if you had a DAC which reclocks with its own internal low jitter clock AND outputs only a word clock (not MCLK), AND you don't want to modify the DAC to get at the MCLK. In this case the only choice for syncing the SB would be a PLL clock multiplier on the word clock from the DAC. (it would be a LOT easier to just grab the MCLK but you have to modify the DAC if you want to that). As has been mentioned already, once you do the external modification you cannot run the SB on its own, the MCLK from the external source HAS to be running for the SB to operate correctly. If this clock is not running when the SB boots up it can get in some really bizzare modes where the data stream gets out of sync with the LRCLK. (don't ask how I know about that!) Then there is the issue of 48/44.1. If you do this for just 11.2896, you have the synchronous reclocking for 44.1, but not for 48, if you ever feed 48 source into the SB you will need some method for telling the DAC to not run in synchronous reclocking mode. I've actually dealt with this by having both 11.2896 and 12.288 clocks on the DAC and sending both to the SB, then sending the MCLK going to the SB's DAC chip to my DAC. The FPGA in the DAC then figures out which one the SB is using and selects the right clock to send to the reclocker. This works very well but is some what complicated. John S. -- JohnSwenson ------------------------------------------------------------------------ JohnSwenson's Profile: http://forums.slimdevices.com/member.php?userid=5974 View this thread: http://forums.slimdevices.com/showthread.php?t=32761 _______________________________________________ audiophiles mailing list audiophiles@lists.slimdevices.com http://lists.slimdevices.com/lists/listinfo/audiophiles
