AndyC_772;207692 Wrote: > The topology is dead simple, really - in an ideal world you'd connect > the clock directly to the DAC board, as close to the pin of the D/A > converter chip itself as you can. The I2S SCK signal should be an > output from the DAC board.
Well, we're done. In the real world, and most of the time, connecting the clock at the DAC is no more than wishful thinking. Or a myth. > ... there has to be a clock divider or PLL somewhere in the system, and > that may mean putting the super-clock on the SB board after all. In > this case, using I2S is still a theoretical improvement over SPDIF, but > it's not giving you the ideal minimum-jitter performance you could have > if the SB were able to directly accept the I2S clock. This is moot. The wire length between I2S output from the Xilinx and the I2S input on the DAC board will be something like two inches. Not a reason for a dirty layout and cabling, yet easy to deal with. Also, assuming you got a near to perfect bitclock and wordclock at DAC pins, you'll still have to face issues regarding how to slave the "transport" (whatever the way it's implemented) and to get back the datas from it. Clocking the DAC instead of the transport is quite impossible when modding existing devices, and even if it's possible in a design from scratch, it's not a panacea. JLM -- jlmatrat ------------------------------------------------------------------------ jlmatrat's Profile: http://forums.slimdevices.com/member.php?userid=10656 View this thread: http://forums.slimdevices.com/showthread.php?t=35642 _______________________________________________ audiophiles mailing list audiophiles@lists.slimdevices.com http://lists.slimdevices.com/lists/listinfo/audiophiles
