Phil, There is a paper around (to which I have lost the link) that examines how S/PDIF clock recovery operates when the input circuity has limited bandwidth (as all real world circuits do). One of the results of the analyis is that the jitter of the recovered clock is indeed correlated to the data on the link. As far as I can remember the reasoning, with non-zero risetimes, The biphase mark encoding of the SPDIF transmission process causes 1s to be detected at a slightly different point to 0s.
The most compelling part of the analysis was that the program material was clearly audiable on the PLL loop control voltage. The implication being that code correlated phase jitter on the SPDIF datastream was being 'demodulated' by the PLL. The authors speculated that jitter correlated to program material was likely to be more audiable than random jitter. Andy. -- Andy8421 ------------------------------------------------------------------------ Andy8421's Profile: http://forums.slimdevices.com/member.php?userid=16846 View this thread: http://forums.slimdevices.com/showthread.php?t=74721 _______________________________________________ audiophiles mailing list audiophiles@lists.slimdevices.com http://lists.slimdevices.com/mailman/listinfo/audiophiles
