The ADC can definitely sample at 1.6 MHz, that is four channels could go up to 400 kHz each (sequentially). The 1.6 MHz correspond to the minimal 15 steps for one sample when setting the ADC clock to 24 MHz, that is, setting the CLKDIV register to zero, and not to 7 as it is set by default (which explains your 200kHz theoretical sampling rate). I have my own assembler code which works, but as it is a bit older, it is not in line with newer things like libpruio. If you want to have a look at my code to get it working let me know and I'll send it to you.
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