commit 46502e37f81028104e34a1e2f3f1eee97dd478a9 Author: Robert Khasanov Date: Mon Aug 18 17:49:52 2014 +0400 [x86] Enable broadwell target in clang. Added -madx option diff --git a/include/clang/Driver/Options.td b/include/clang/Driver/Options.td index 0d5b1b7..fd4f322 100644 --- a/include/clang/Driver/Options.td +++ b/include/clang/Driver/Options.td @@ -1117,40 +1117,41 @@ def mno_avx512f : Flag<["-"], "mno-avx512f">, Group; def mno_avx512cd : Flag<["-"], "mno-avx512cd">, Group; def mno_avx512er : Flag<["-"], "mno-avx512er">, Group; def mno_avx512pf : Flag<["-"], "mno-avx512pf">, Group; def mno_avx512dq : Flag<["-"], "mno-avx512dq">, Group; def mno_avx512bw : Flag<["-"], "mno-avx512bw">, Group; def mno_avx512vl : Flag<["-"], "mno-avx512vl">, Group; def mno_pclmul : Flag<["-"], "mno-pclmul">, Group; def mno_lzcnt : Flag<["-"], "mno-lzcnt">, Group; def mno_rdrnd : Flag<["-"], "mno-rdrnd">, Group; def mno_bmi : Flag<["-"], "mno-bmi">, Group; def mno_bmi2 : Flag<["-"], "mno-bmi2">, Group; def mno_popcnt : Flag<["-"], "mno-popcnt">, Group; def mno_tbm : Flag<["-"], "mno-tbm">, Group; def mno_fma4 : Flag<["-"], "mno-fma4">, Group; def mno_fma : Flag<["-"], "mno-fma">, Group; def mno_xop : Flag<["-"], "mno-xop">, Group; def mno_f16c : Flag<["-"], "mno-f16c">, Group; def mno_rtm : Flag<["-"], "mno-rtm">, Group; def mno_prfchw : Flag<["-"], "mno-prfchw">, Group; def mno_rdseed : Flag<["-"], "mno-rdseed">, Group; +def mno_adx : Flag<["-"], "mno-adx">, Group; def mno_sha : Flag<["-"], "mno-sha">, Group; def munaligned_access : Flag<["-"], "munaligned-access">, Group, HelpText<"Allow memory accesses to be unaligned (AArch32/AArch64 only)">; def mno_unaligned_access : Flag<["-"], "mno-unaligned-access">, Group, HelpText<"Force all memory accesses to be aligned (AArch32/AArch64 only)">; def mstrict_align : Flag<["-"], "mstrict-align">, Alias, Flags<[CC1Option,HelpHidden]>, HelpText<"Force all memory accesses to be aligned (same as mno-unaligned-access)">; def mno_thumb : Flag<["-"], "mno-thumb">, Group; def mrestrict_it: Flag<["-"], "mrestrict-it">, Group, HelpText<"Disallow generation of deprecated IT blocks for ARMv8. It is on by default for ARMv8 Thumb mode.">; def mno_restrict_it: Flag<["-"], "mno-restrict-it">, Group, HelpText<"Allow generation of deprecated IT blocks for ARMv8. It is off by default for ARMv8 Thumb mode">; def marm : Flag<["-"], "marm">, Alias; def ffixed_r9 : Flag<["-"], "ffixed-r9">, Group, HelpText<"Reserve the r9 register (ARM only)">; def mcrc : Flag<["-"], "mcrc">, Group, HelpText<"Allow use of CRC instructions (ARM only)">; def mnocrc : Flag<["-"], "mnocrc">, Group, HelpText<"Disallow use of CRC instructions (ARM only)">; @@ -1214,40 +1215,41 @@ def mavx512f : Flag<["-"], "mavx512f">, Group; def mavx512cd : Flag<["-"], "mavx512cd">, Group; def mavx512er : Flag<["-"], "mavx512er">, Group; def mavx512pf : Flag<["-"], "mavx512pf">, Group; def mavx512dq : Flag<["-"], "mavx512dq">, Group; def mavx512bw : Flag<["-"], "mavx512bw">, Group; def mavx512vl : Flag<["-"], "mavx512vl">, Group; def mpclmul : Flag<["-"], "mpclmul">, Group; def mlzcnt : Flag<["-"], "mlzcnt">, Group; def mrdrnd : Flag<["-"], "mrdrnd">, Group; def mbmi : Flag<["-"], "mbmi">, Group; def mbmi2 : Flag<["-"], "mbmi2">, Group; def mpopcnt : Flag<["-"], "mpopcnt">, Group; def mtbm : Flag<["-"], "mtbm">, Group; def mfma4 : Flag<["-"], "mfma4">, Group; def mfma : Flag<["-"], "mfma">, Group; def mxop : Flag<["-"], "mxop">, Group; def mf16c : Flag<["-"], "mf16c">, Group; def mrtm : Flag<["-"], "mrtm">, Group; def mprfchw : Flag<["-"], "mprfchw">, Group; def mrdseed : Flag<["-"], "mrdseed">, Group; +def madx : Flag<["-"], "madx">, Group; def msha : Flag<["-"], "msha">, Group; def mcx16 : Flag<["-"], "mcx16">, Group; def mips16 : Flag<["-"], "mips16">, Group; def mno_mips16 : Flag<["-"], "mno-mips16">, Group; def mmicromips : Flag<["-"], "mmicromips">, Group; def mno_micromips : Flag<["-"], "mno-micromips">, Group; def mxgot : Flag<["-"], "mxgot">, Group; def mno_xgot : Flag<["-"], "mno-xgot">, Group; def mldc1_sdc1 : Flag<["-"], "mldc1-sdc1">, Group; def mno_ldc1_sdc1 : Flag<["-"], "mno-ldc1-sdc1">, Group; def mcheck_zero_division : Flag<["-"], "mcheck-zero-division">, Group; def mno_check_zero_division : Flag<["-"], "mno-check-zero-division">, Group; def mdsp : Flag<["-"], "mdsp">, Group; def mno_dsp : Flag<["-"], "mno-dsp">, Group; def mdspr2 : Flag<["-"], "mdspr2">, Group; def mno_dspr2 : Flag<["-"], "mno-dspr2">, Group; def msingle_float : Flag<["-"], "msingle-float">, Group; def mdouble_float : Flag<["-"], "mdouble-float">, Group; def mmsa : Flag<["-"], "mmsa">, Group, diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp index f4bf89d..5335443 100644 --- a/lib/Basic/Targets.cpp +++ b/lib/Basic/Targets.cpp @@ -1660,40 +1660,41 @@ class X86TargetInfo : public TargetInfo { enum MMX3DNowEnum { NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon } MMX3DNowLevel; enum XOPEnum { NoXOP, SSE4A, FMA4, XOP } XOPLevel; bool HasAES; bool HasPCLMUL; bool HasLZCNT; bool HasRDRND; bool HasBMI; bool HasBMI2; bool HasPOPCNT; bool HasRTM; bool HasPRFCHW; bool HasRDSEED; + bool HasADX; bool HasTBM; bool HasFMA; bool HasF16C; bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW, HasAVX512VL; bool HasSHA; bool HasCX16; /// \brief Enumeration of all of the X86 CPUs supported by Clang. /// /// Each enumeration represents a particular CPU supported by Clang. These /// loosely correspond to the options passed to '-march' or '-mtune' flags. enum CPUKind { CK_Generic, /// \name i386 /// i386-generation processors. //@{ CK_i386, //@} @@ -1749,40 +1750,41 @@ class X86TargetInfo : public TargetInfo { /// codename which GCC no longer accepts as an option to -march, but Clang /// has some logic for recognizing it. // FIXME: Warn, deprecate, and potentially remove this. CK_Penryn, //@} /// \name Atom /// Atom processors //@{ CK_Atom, CK_Silvermont, //@} /// \name Nehalem /// Nehalem microarchitecture based processors. //@{ CK_Corei7, CK_Corei7AVX, CK_CoreAVXi, CK_CoreAVX2, + CK_Broadwell, //@} /// \name Knights Landing /// Knights Landing processor. CK_KNL, /// \name Skylake Server /// Skylake server processor. CK_SKX, /// \name K6 /// K6 architecture processors. //@{ CK_K6, CK_K6_2, CK_K6_3, //@} /// \name K7 /// K7 architecture processors. @@ -1830,45 +1832,45 @@ class X86TargetInfo : public TargetInfo { //@} /// \name Geode /// Geode processors. //@{ CK_Geode //@} } CPU; enum FPMathKind { FP_Default, FP_SSE, FP_387 } FPMath; public: X86TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false), - HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasTBM(false), - HasFMA(false), HasF16C(false), HasAVX512CD(false), HasAVX512ER(false), - HasAVX512PF(false), HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false), - HasSHA(false), HasCX16(false), CPU(CK_Generic), - FPMath(FP_Default) { + HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasADX(false), + HasTBM(false), HasFMA(false), HasF16C(false), HasAVX512CD(false), + HasAVX512ER(false), HasAVX512PF(false), HasAVX512DQ(false), + HasAVX512BW(false), HasAVX512VL(false), HasSHA(false), HasCX16(false), + CPU(CK_Generic), FPMath(FP_Default) { BigEndian = false; LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; } unsigned getFloatEvalMethod() const override { // X87 evaluates with 80 bits "long double" precision. return SSELevel == NoSSE ? 2 : 0; } void getTargetBuiltins(const Builtin::Info *&Records, unsigned &NumRecords) const override { Records = BuiltinInfo; NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; } void getGCCRegNames(const char * const *&Names, unsigned &NumNames) const override { Names = GCCRegNames; NumNames = llvm::array_lengthof(GCCRegNames); } void getGCCRegAliases(const GCCRegAlias *&Aliases, unsigned &NumAliases) const override { Aliases = nullptr; @@ -1926,40 +1928,41 @@ public: .Case("i686", CK_i686) .Case("pentiumpro", CK_PentiumPro) .Case("pentium2", CK_Pentium2) .Case("pentium3", CK_Pentium3) .Case("pentium3m", CK_Pentium3M) .Case("pentium-m", CK_PentiumM) .Case("c3-2", CK_C3_2) .Case("yonah", CK_Yonah) .Case("pentium4", CK_Pentium4) .Case("pentium4m", CK_Pentium4M) .Case("prescott", CK_Prescott) .Case("nocona", CK_Nocona) .Case("core2", CK_Core2) .Case("penryn", CK_Penryn) .Case("atom", CK_Atom) .Case("slm", CK_Silvermont) .Case("corei7", CK_Corei7) .Case("corei7-avx", CK_Corei7AVX) .Case("core-avx-i", CK_CoreAVXi) .Case("core-avx2", CK_CoreAVX2) + .Case("broadwell", CK_Broadwell) .Case("knl", CK_KNL) .Case("skx", CK_SKX) .Case("k6", CK_K6) .Case("k6-2", CK_K6_2) .Case("k6-3", CK_K6_3) .Case("athlon", CK_Athlon) .Case("athlon-tbird", CK_AthlonThunderbird) .Case("athlon-4", CK_Athlon4) .Case("athlon-xp", CK_AthlonXP) .Case("athlon-mp", CK_AthlonMP) .Case("athlon64", CK_Athlon64) .Case("athlon64-sse3", CK_Athlon64SSE3) .Case("athlon-fx", CK_AthlonFX) .Case("k8", CK_K8) .Case("k8-sse3", CK_K8SSE3) .Case("opteron", CK_Opteron) .Case("opteron-sse3", CK_OpteronSSE3) .Case("amdfam10", CK_AMDFAM10) .Case("btver1", CK_BTVER1) .Case("btver2", CK_BTVER2) @@ -2005,40 +2008,41 @@ public: case CK_Athlon: case CK_AthlonThunderbird: case CK_Athlon4: case CK_AthlonXP: case CK_AthlonMP: case CK_Geode: // Only accept certain architectures when compiling in 32-bit mode. if (getTriple().getArch() != llvm::Triple::x86) return false; // Fallthrough case CK_Nocona: case CK_Core2: case CK_Penryn: case CK_Atom: case CK_Silvermont: case CK_Corei7: case CK_Corei7AVX: case CK_CoreAVXi: case CK_CoreAVX2: + case CK_Broadwell: case CK_KNL: case CK_SKX: case CK_Athlon64: case CK_Athlon64SSE3: case CK_AthlonFX: case CK_K8: case CK_K8SSE3: case CK_Opteron: case CK_OpteronSSE3: case CK_AMDFAM10: case CK_BTVER1: case CK_BTVER2: case CK_BDVER1: case CK_BDVER2: case CK_BDVER3: case CK_BDVER4: case CK_x86_64: return true; } llvm_unreachable("Unhandled CPU kind"); @@ -2140,70 +2144,89 @@ void X86TargetInfo::getDefaultFeatures(llvm::StringMap &Features) const { case CK_CoreAVXi: setFeatureEnabledImpl(Features, "avx", true); setFeatureEnabledImpl(Features, "aes", true); setFeatureEnabledImpl(Features, "pclmul", true); setFeatureEnabledImpl(Features, "rdrnd", true); setFeatureEnabledImpl(Features, "f16c", true); break; case CK_CoreAVX2: setFeatureEnabledImpl(Features, "avx2", true); setFeatureEnabledImpl(Features, "aes", true); setFeatureEnabledImpl(Features, "pclmul", true); setFeatureEnabledImpl(Features, "lzcnt", true); setFeatureEnabledImpl(Features, "rdrnd", true); setFeatureEnabledImpl(Features, "f16c", true); setFeatureEnabledImpl(Features, "bmi", true); setFeatureEnabledImpl(Features, "bmi2", true); setFeatureEnabledImpl(Features, "rtm", true); setFeatureEnabledImpl(Features, "fma", true); setFeatureEnabledImpl(Features, "cx16", true); break; + case CK_Broadwell: + setFeatureEnabledImpl(Features, "avx2", true); + setFeatureEnabledImpl(Features, "aes", true); + setFeatureEnabledImpl(Features, "pclmul", true); + setFeatureEnabledImpl(Features, "lzcnt", true); + setFeatureEnabledImpl(Features, "rdrnd", true); + setFeatureEnabledImpl(Features, "f16c", true); + setFeatureEnabledImpl(Features, "bmi", true); + setFeatureEnabledImpl(Features, "bmi2", true); + setFeatureEnabledImpl(Features, "rtm", true); + setFeatureEnabledImpl(Features, "fma", true); + setFeatureEnabledImpl(Features, "cx16", true); + setFeatureEnabledImpl(Features, "rdseed", true); + setFeatureEnabledImpl(Features, "adx", true); + break; case CK_KNL: setFeatureEnabledImpl(Features, "avx512f", true); setFeatureEnabledImpl(Features, "avx512cd", true); setFeatureEnabledImpl(Features, "avx512er", true); setFeatureEnabledImpl(Features, "avx512pf", true); setFeatureEnabledImpl(Features, "aes", true); setFeatureEnabledImpl(Features, "pclmul", true); setFeatureEnabledImpl(Features, "lzcnt", true); setFeatureEnabledImpl(Features, "rdrnd", true); setFeatureEnabledImpl(Features, "f16c", true); setFeatureEnabledImpl(Features, "bmi", true); setFeatureEnabledImpl(Features, "bmi2", true); setFeatureEnabledImpl(Features, "rtm", true); setFeatureEnabledImpl(Features, "fma", true); + setFeatureEnabledImpl(Features, "rdseed", true); + setFeatureEnabledImpl(Features, "adx", true); break; case CK_SKX: setFeatureEnabledImpl(Features, "avx512f", true); setFeatureEnabledImpl(Features, "avx512cd", true); setFeatureEnabledImpl(Features, "avx512dq", true); setFeatureEnabledImpl(Features, "avx512bw", true); setFeatureEnabledImpl(Features, "avx512vl", true); setFeatureEnabledImpl(Features, "aes", true); setFeatureEnabledImpl(Features, "pclmul", true); setFeatureEnabledImpl(Features, "lzcnt", true); setFeatureEnabledImpl(Features, "rdrnd", true); setFeatureEnabledImpl(Features, "f16c", true); setFeatureEnabledImpl(Features, "bmi", true); setFeatureEnabledImpl(Features, "bmi2", true); setFeatureEnabledImpl(Features, "rtm", true); setFeatureEnabledImpl(Features, "fma", true); + setFeatureEnabledImpl(Features, "rdseed", true); + setFeatureEnabledImpl(Features, "adx", true); break; case CK_K6: case CK_WinChipC6: setFeatureEnabledImpl(Features, "mmx", true); break; case CK_K6_2: case CK_K6_3: case CK_WinChip2: case CK_C3: setFeatureEnabledImpl(Features, "3dnow", true); break; case CK_Athlon: case CK_AthlonThunderbird: case CK_Geode: setFeatureEnabledImpl(Features, "3dnowa", true); break; case CK_Athlon4: case CK_AthlonXP: case CK_AthlonMP: setFeatureEnabledImpl(Features, "sse", true); @@ -2496,40 +2519,45 @@ bool X86TargetInfo::handleTargetFeatures(std::vector &Features, if (Feature == "popcnt") { HasPOPCNT = true; continue; } if (Feature == "rtm") { HasRTM = true; continue; } if (Feature == "prfchw") { HasPRFCHW = true; continue; } if (Feature == "rdseed") { HasRDSEED = true; continue; } + if (Feature == "adx") { + HasADX = true; + continue; + } + if (Feature == "tbm") { HasTBM = true; continue; } if (Feature == "fma") { HasFMA = true; continue; } if (Feature == "f16c") { HasF16C = true; continue; } if (Feature == "avx512cd") { HasAVX512CD = true; continue; } @@ -2706,40 +2734,41 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, break; case CK_Yonah: case CK_Prescott: case CK_Nocona: defineCPUMacros(Builder, "nocona"); break; case CK_Core2: case CK_Penryn: defineCPUMacros(Builder, "core2"); break; case CK_Atom: defineCPUMacros(Builder, "atom"); break; case CK_Silvermont: defineCPUMacros(Builder, "slm"); break; case CK_Corei7: case CK_Corei7AVX: case CK_CoreAVXi: case CK_CoreAVX2: + case CK_Broadwell: defineCPUMacros(Builder, "corei7"); break; case CK_KNL: defineCPUMacros(Builder, "knl"); break; case CK_SKX: defineCPUMacros(Builder, "skx"); break; case CK_K6_2: Builder.defineMacro("__k6_2__"); Builder.defineMacro("__tune_k6_2__"); // Fallthrough case CK_K6_3: if (CPU != CK_K6_2) { // In case of fallthrough // FIXME: GCC may be enabling these in cases where some other k6 // architecture is specified but -m3dnow is explicitly provided. The // exact semantics need to be determined and emulated here. Builder.defineMacro("__k6_3__"); Builder.defineMacro("__tune_k6_3__"); } @@ -2815,40 +2844,43 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__RDRND__"); if (HasBMI) Builder.defineMacro("__BMI__"); if (HasBMI2) Builder.defineMacro("__BMI2__"); if (HasPOPCNT) Builder.defineMacro("__POPCNT__"); if (HasRTM) Builder.defineMacro("__RTM__"); if (HasPRFCHW) Builder.defineMacro("__PRFCHW__"); if (HasRDSEED) Builder.defineMacro("__RDSEED__"); + if (HasADX) + Builder.defineMacro("__ADX__"); + if (HasTBM) Builder.defineMacro("__TBM__"); switch (XOPLevel) { case XOP: Builder.defineMacro("__XOP__"); case FMA4: Builder.defineMacro("__FMA4__"); case SSE4A: Builder.defineMacro("__SSE4A__"); case NoXOP: break; } if (HasFMA) Builder.defineMacro("__FMA__"); if (HasF16C) Builder.defineMacro("__F16C__"); diff --git a/test/Preprocessor/predefined-arch-macros.c b/test/Preprocessor/predefined-arch-macros.c index 4d05212..5f53809 100644 --- a/test/Preprocessor/predefined-arch-macros.c +++ b/test/Preprocessor/predefined-arch-macros.c @@ -545,40 +545,104 @@ // CHECK_CORE_AVX2_M64: #define __PCLMUL__ 1 // CHECK_CORE_AVX2_M64: #define __POPCNT__ 1 // CHECK_CORE_AVX2_M64: #define __RDRND__ 1 // CHECK_CORE_AVX2_M64: #define __RTM__ 1 // CHECK_CORE_AVX2_M64: #define __SSE2_MATH__ 1 // CHECK_CORE_AVX2_M64: #define __SSE2__ 1 // CHECK_CORE_AVX2_M64: #define __SSE3__ 1 // CHECK_CORE_AVX2_M64: #define __SSE4_1__ 1 // CHECK_CORE_AVX2_M64: #define __SSE4_2__ 1 // CHECK_CORE_AVX2_M64: #define __SSE_MATH__ 1 // CHECK_CORE_AVX2_M64: #define __SSE__ 1 // CHECK_CORE_AVX2_M64: #define __SSSE3__ 1 // CHECK_CORE_AVX2_M64: #define __amd64 1 // CHECK_CORE_AVX2_M64: #define __amd64__ 1 // CHECK_CORE_AVX2_M64: #define __corei7 1 // CHECK_CORE_AVX2_M64: #define __corei7__ 1 // CHECK_CORE_AVX2_M64: #define __tune_corei7__ 1 // CHECK_CORE_AVX2_M64: #define __x86_64 1 // CHECK_CORE_AVX2_M64: #define __x86_64__ 1 // +// RUN: %clang -march=broadwell -m32 -E -dM %s -o - 2>&1 \ +// RUN: -target i386-unknown-linux \ +// RUN: | FileCheck %s -check-prefix=CHECK_BROADWELL_M32 +// CHECK_BROADWELL_M32: #define __ADX__ 1 +// CHECK_BROADWELL_M32: #define __AES__ 1 +// CHECK_BROADWELL_M32: #define __AVX2__ 1 +// CHECK_BROADWELL_M32: #define __AVX__ 1 +// CHECK_BROADWELL_M32: #define __BMI2__ 1 +// CHECK_BROADWELL_M32: #define __BMI__ 1 +// CHECK_BROADWELL_M32: #define __F16C__ 1 +// CHECK_BROADWELL_M32: #define __FMA__ 1 +// CHECK_BROADWELL_M32: #define __LZCNT__ 1 +// CHECK_BROADWELL_M32: #define __MMX__ 1 +// CHECK_BROADWELL_M32: #define __PCLMUL__ 1 +// CHECK_BROADWELL_M32: #define __POPCNT__ 1 +// CHECK_BROADWELL_M32: #define __RDRND__ 1 +// CHECK_BROADWELL_M32: #define __RDSEED__ 1 +// CHECK_BROADWELL_M32: #define __RTM__ 1 +// CHECK_BROADWELL_M32: #define __SSE2__ 1 +// CHECK_BROADWELL_M32: #define __SSE3__ 1 +// CHECK_BROADWELL_M32: #define __SSE4_1__ 1 +// CHECK_BROADWELL_M32: #define __SSE4_2__ 1 +// CHECK_BROADWELL_M32: #define __SSE__ 1 +// CHECK_BROADWELL_M32: #define __SSSE3__ 1 +// CHECK_BROADWELL_M32: #define __corei7 1 +// CHECK_BROADWELL_M32: #define __corei7__ 1 +// CHECK_BROADWELL_M32: #define __i386 1 +// CHECK_BROADWELL_M32: #define __i386__ 1 +// CHECK_BROADWELL_M32: #define __tune_corei7__ 1 +// CHECK_BROADWELL_M32: #define i386 1 +// RUN: %clang -march=broadwell -m64 -E -dM %s -o - 2>&1 \ +// RUN: -target i386-unknown-linux \ +// RUN: | FileCheck %s -check-prefix=CHECK_BROADWELL_M64 +// CHECK_BROADWELL_M64: #define __ADX__ 1 +// CHECK_BROADWELL_M64: #define __AES__ 1 +// CHECK_BROADWELL_M64: #define __AVX2__ 1 +// CHECK_BROADWELL_M64: #define __AVX__ 1 +// CHECK_BROADWELL_M64: #define __BMI2__ 1 +// CHECK_BROADWELL_M64: #define __BMI__ 1 +// CHECK_BROADWELL_M64: #define __F16C__ 1 +// CHECK_BROADWELL_M64: #define __FMA__ 1 +// CHECK_BROADWELL_M64: #define __LZCNT__ 1 +// CHECK_BROADWELL_M64: #define __MMX__ 1 +// CHECK_BROADWELL_M64: #define __PCLMUL__ 1 +// CHECK_BROADWELL_M64: #define __POPCNT__ 1 +// CHECK_BROADWELL_M64: #define __RDRND__ 1 +// CHECK_BROADWELL_M64: #define __RDSEED__ 1 +// CHECK_BROADWELL_M64: #define __RTM__ 1 +// CHECK_BROADWELL_M64: #define __SSE2_MATH__ 1 +// CHECK_BROADWELL_M64: #define __SSE2__ 1 +// CHECK_BROADWELL_M64: #define __SSE3__ 1 +// CHECK_BROADWELL_M64: #define __SSE4_1__ 1 +// CHECK_BROADWELL_M64: #define __SSE4_2__ 1 +// CHECK_BROADWELL_M64: #define __SSE_MATH__ 1 +// CHECK_BROADWELL_M64: #define __SSE__ 1 +// CHECK_BROADWELL_M64: #define __SSSE3__ 1 +// CHECK_BROADWELL_M64: #define __amd64 1 +// CHECK_BROADWELL_M64: #define __amd64__ 1 +// CHECK_BROADWELL_M64: #define __corei7 1 +// CHECK_BROADWELL_M64: #define __corei7__ 1 +// CHECK_BROADWELL_M64: #define __tune_corei7__ 1 +// CHECK_BROADWELL_M64: #define __x86_64 1 +// CHECK_BROADWELL_M64: #define __x86_64__ 1 +// // RUN: %clang -march=knl -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck %s -check-prefix=CHECK_KNL_M32 // CHECK_KNL_M32: #define __AES__ 1 // CHECK_KNL_M32: #define __AVX2__ 1 // CHECK_KNL_M32: #define __AVX512CD__ 1 // CHECK_KNL_M32: #define __AVX512ER__ 1 // CHECK_KNL_M32: #define __AVX512F__ 1 // CHECK_KNL_M32: #define __AVX512PF__ 1 // CHECK_KNL_M32: #define __AVX__ 1 // CHECK_KNL_M32: #define __BMI2__ 1 // CHECK_KNL_M32: #define __BMI__ 1 // CHECK_KNL_M32: #define __F16C__ 1 // CHECK_KNL_M32: #define __FMA__ 1 // CHECK_KNL_M32: #define __LZCNT__ 1 // CHECK_KNL_M32: #define __MMX__ 1 // CHECK_KNL_M32: #define __PCLMUL__ 1 // CHECK_KNL_M32: #define __POPCNT__ 1 // CHECK_KNL_M32: #define __RDRND__ 1 // CHECK_KNL_M32: #define __RTM__ 1 diff --git a/test/Preprocessor/x86_target_features.c b/test/Preprocessor/x86_target_features.c index 23fa493..806eeec 100644 --- a/test/Preprocessor/x86_target_features.c +++ b/test/Preprocessor/x86_target_features.c @@ -264,20 +264,28 @@ // RUN: %clang -target i386-unknown-unknown -march=atom -mprfchw -x c -E -dM -o - %s | FileCheck --check-prefix=PRFCHW %s // PRFCHW: #define __PRFCHW__ 1 // RUN: %clang -target i386-unknown-unknown -march=btver2 -mno-prfchw -x c -E -dM -o - %s | FileCheck --check-prefix=NOPRFCHW %s // NOPRFCHW-NOT: #define __PRFCHW__ 1 // RUN: %clang -target i386-unknown-unknown -march=atom -m3dnow -x c -E -dM -o - %s | FileCheck --check-prefix=3DNOWPRFCHW %s // 3DNOWPRFCHW: #define __PRFCHW__ 1 // RUN: %clang -target i386-unknown-unknown -march=atom -mno-prfchw -m3dnow -x c -E -dM -o - %s | FileCheck --check-prefix=3DNOWNOPRFCHW %s // 3DNOWNOPRFCHW-NOT: #define __PRFCHW__ 1 // RUN: %clang -target i386-unknown-unknown -march=atom -mprfchw -mno-3dnow -x c -E -dM -o - %s | FileCheck --check-prefix=NO3DNOWPRFCHW %s // NO3DNOWPRFCHW: #define __PRFCHW__ 1 +// RUN: %clang -target i386-unknown-unknown -march=atom -madx -x c -E -dM -o - %s | FileCheck --check-prefix=ADX %s + +// ADX: #define __ADX__ 1 + +// RUN: %clang -target i386-unknown-unknown -march=atom -mrdseed -x c -E -dM -o - %s | FileCheck --check-prefix=RDSEED %s + +// RDSEED: #define __RDSEED__ 1 +