Author: Alexandros Lamprineas
Date: 2025-01-23T17:55:03Z
New Revision: 5a7d92f7a09d5580a298c2982bd42918b7ec492c

URL: 
https://github.com/llvm/llvm-project/commit/5a7d92f7a09d5580a298c2982bd42918b7ec492c
DIFF: 
https://github.com/llvm/llvm-project/commit/5a7d92f7a09d5580a298c2982bd42918b7ec492c.diff

LOG: [NFC] Remove invalid features from test and autogenerate checks. (#124130)

Added: 
    

Modified: 
    clang/test/CodeGen/AArch64/cpu-supports-target.c

Removed: 
    


################################################################################
diff  --git a/clang/test/CodeGen/AArch64/cpu-supports-target.c 
b/clang/test/CodeGen/AArch64/cpu-supports-target.c
index b185dda2881080..6223db7c092534 100644
--- a/clang/test/CodeGen/AArch64/cpu-supports-target.c
+++ b/clang/test/CodeGen/AArch64/cpu-supports-target.c
@@ -1,27 +1,150 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 
UTC_ARGS: --check-attributes --check-globals all --version 5
 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -o - %s | 
FileCheck %s
 
-int check_all_feature() {
+//.
+// CHECK: @__aarch64_cpu_features = external dso_local global { i64 }
+//.
+// CHECK: Function Attrs: noinline nounwind optnone
+// CHECK-LABEL: define dso_local i32 @check_all_features(
+// CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
+// CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 66367
+// CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 66367
+// CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
+// CHECK-NEXT:    br i1 [[TMP3]], label %[[IF_THEN:.*]], label %[[IF_ELSE:.*]]
+// CHECK:       [[IF_THEN]]:
+// CHECK-NEXT:    store i32 1, ptr [[RETVAL]], align 4
+// CHECK-NEXT:    br label %[[RETURN:.*]]
+// CHECK:       [[IF_ELSE]]:
+// CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
+// CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 14272
+// CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 14272
+// CHECK-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
+// CHECK-NEXT:    br i1 [[TMP7]], label %[[IF_THEN1:.*]], label 
%[[IF_ELSE2:.*]]
+// CHECK:       [[IF_THEN1]]:
+// CHECK-NEXT:    store i32 2, ptr [[RETVAL]], align 4
+// CHECK-NEXT:    br label %[[RETURN]]
+// CHECK:       [[IF_ELSE2]]:
+// CHECK-NEXT:    [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
+// CHECK-NEXT:    [[TMP9:%.*]] = and i64 [[TMP8]], 2065152
+// CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 2065152
+// CHECK-NEXT:    [[TMP11:%.*]] = and i1 true, [[TMP10]]
+// CHECK-NEXT:    br i1 [[TMP11]], label %[[IF_THEN3:.*]], label 
%[[IF_ELSE4:.*]]
+// CHECK:       [[IF_THEN3]]:
+// CHECK-NEXT:    store i32 3, ptr [[RETVAL]], align 4
+// CHECK-NEXT:    br label %[[RETURN]]
+// CHECK:       [[IF_ELSE4]]:
+// CHECK-NEXT:    [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 
8
+// CHECK-NEXT:    [[TMP13:%.*]] = and i64 [[TMP12]], 288230376183169792
+// CHECK-NEXT:    [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 288230376183169792
+// CHECK-NEXT:    [[TMP15:%.*]] = and i1 true, [[TMP14]]
+// CHECK-NEXT:    br i1 [[TMP15]], label %[[IF_THEN5:.*]], label 
%[[IF_ELSE6:.*]]
+// CHECK:       [[IF_THEN5]]:
+// CHECK-NEXT:    store i32 4, ptr [[RETVAL]], align 4
+// CHECK-NEXT:    br label %[[RETURN]]
+// CHECK:       [[IF_ELSE6]]:
+// CHECK-NEXT:    [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 
8
+// CHECK-NEXT:    [[TMP17:%.*]] = and i64 [[TMP16]], 1275134720
+// CHECK-NEXT:    [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 1275134720
+// CHECK-NEXT:    [[TMP19:%.*]] = and i1 true, [[TMP18]]
+// CHECK-NEXT:    br i1 [[TMP19]], label %[[IF_THEN7:.*]], label 
%[[IF_ELSE8:.*]]
+// CHECK:       [[IF_THEN7]]:
+// CHECK-NEXT:    store i32 5, ptr [[RETVAL]], align 4
+// CHECK-NEXT:    br label %[[RETURN]]
+// CHECK:       [[IF_ELSE8]]:
+// CHECK-NEXT:    [[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align 
8
+// CHECK-NEXT:    [[TMP21:%.*]] = and i64 [[TMP20]], 52814742272
+// CHECK-NEXT:    [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 52814742272
+// CHECK-NEXT:    [[TMP23:%.*]] = and i1 true, [[TMP22]]
+// CHECK-NEXT:    br i1 [[TMP23]], label %[[IF_THEN9:.*]], label 
%[[IF_ELSE10:.*]]
+// CHECK:       [[IF_THEN9]]:
+// CHECK-NEXT:    store i32 6, ptr [[RETVAL]], align 4
+// CHECK-NEXT:    br label %[[RETURN]]
+// CHECK:       [[IF_ELSE10]]:
+// CHECK-NEXT:    [[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 
8
+// CHECK-NEXT:    [[TMP25:%.*]] = and i64 [[TMP24]], 344671224576
+// CHECK-NEXT:    [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 344671224576
+// CHECK-NEXT:    [[TMP27:%.*]] = and i1 true, [[TMP26]]
+// CHECK-NEXT:    br i1 [[TMP27]], label %[[IF_THEN11:.*]], label 
%[[IF_ELSE12:.*]]
+// CHECK:       [[IF_THEN11]]:
+// CHECK-NEXT:    store i32 7, ptr [[RETVAL]], align 4
+// CHECK-NEXT:    br label %[[RETURN]]
+// CHECK:       [[IF_ELSE12]]:
+// CHECK-NEXT:    [[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 
8
+// CHECK-NEXT:    [[TMP29:%.*]] = and i64 [[TMP28]], 3918083994400
+// CHECK-NEXT:    [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 3918083994400
+// CHECK-NEXT:    [[TMP31:%.*]] = and i1 true, [[TMP30]]
+// CHECK-NEXT:    br i1 [[TMP31]], label %[[IF_THEN13:.*]], label 
%[[IF_ELSE14:.*]]
+// CHECK:       [[IF_THEN13]]:
+// CHECK-NEXT:    store i32 8, ptr [[RETVAL]], align 4
+// CHECK-NEXT:    br label %[[RETURN]]
+// CHECK:       [[IF_ELSE14]]:
+// CHECK-NEXT:    [[TMP32:%.*]] = load i64, ptr @__aarch64_cpu_features, align 
8
+// CHECK-NEXT:    [[TMP33:%.*]] = and i64 [[TMP32]], 92359111017216
+// CHECK-NEXT:    [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 92359111017216
+// CHECK-NEXT:    [[TMP35:%.*]] = and i1 true, [[TMP34]]
+// CHECK-NEXT:    br i1 [[TMP35]], label %[[IF_THEN15:.*]], label 
%[[IF_ELSE16:.*]]
+// CHECK:       [[IF_THEN15]]:
+// CHECK-NEXT:    store i32 9, ptr [[RETVAL]], align 4
+// CHECK-NEXT:    br label %[[RETURN]]
+// CHECK:       [[IF_ELSE16]]:
+// CHECK-NEXT:    [[TMP36:%.*]] = load i64, ptr @__aarch64_cpu_features, align 
8
+// CHECK-NEXT:    [[TMP37:%.*]] = and i64 [[TMP36]], 10836786603360256
+// CHECK-NEXT:    [[TMP38:%.*]] = icmp eq i64 [[TMP37]], 10836786603360256
+// CHECK-NEXT:    [[TMP39:%.*]] = and i1 true, [[TMP38]]
+// CHECK-NEXT:    br i1 [[TMP39]], label %[[IF_THEN17:.*]], label 
%[[IF_ELSE18:.*]]
+// CHECK:       [[IF_THEN17]]:
+// CHECK-NEXT:    store i32 10, ptr [[RETVAL]], align 4
+// CHECK-NEXT:    br label %[[RETURN]]
+// CHECK:       [[IF_ELSE18]]:
+// CHECK-NEXT:    [[TMP40:%.*]] = load i64, ptr @__aarch64_cpu_features, align 
8
+// CHECK-NEXT:    [[TMP41:%.*]] = and i64 [[TMP40]], 54047593709241088
+// CHECK-NEXT:    [[TMP42:%.*]] = icmp eq i64 [[TMP41]], 54047593709241088
+// CHECK-NEXT:    [[TMP43:%.*]] = and i1 true, [[TMP42]]
+// CHECK-NEXT:    br i1 [[TMP43]], label %[[IF_THEN19:.*]], label 
%[[IF_ELSE20:.*]]
+// CHECK:       [[IF_THEN19]]:
+// CHECK-NEXT:    store i32 11, ptr [[RETVAL]], align 4
+// CHECK-NEXT:    br label %[[RETURN]]
+// CHECK:       [[IF_ELSE20]]:
+// CHECK-NEXT:    [[TMP44:%.*]] = load i64, ptr @__aarch64_cpu_features, align 
8
+// CHECK-NEXT:    [[TMP45:%.*]] = and i64 [[TMP44]], 216177180294578944
+// CHECK-NEXT:    [[TMP46:%.*]] = icmp eq i64 [[TMP45]], 216177180294578944
+// CHECK-NEXT:    [[TMP47:%.*]] = and i1 true, [[TMP46]]
+// CHECK-NEXT:    br i1 [[TMP47]], label %[[IF_THEN21:.*]], label 
%[[IF_ELSE22:.*]]
+// CHECK:       [[IF_THEN21]]:
+// CHECK-NEXT:    store i32 12, ptr [[RETVAL]], align 4
+// CHECK-NEXT:    br label %[[RETURN]]
+// CHECK:       [[IF_ELSE22]]:
+// CHECK-NEXT:    store i32 0, ptr [[RETVAL]], align 4
+// CHECK-NEXT:    br label %[[RETURN]]
+// CHECK:       [[RETURN]]:
+// CHECK-NEXT:    [[TMP48:%.*]] = load i32, ptr [[RETVAL]], align 4
+// CHECK-NEXT:    ret i32 [[TMP48]]
+//
+int check_all_features() {
   if (__builtin_cpu_supports("rng+flagm+flagm2+fp16fml+dotprod+sm4"))
     return 1;
-  else if (__builtin_cpu_supports("rdm+lse+fp+simd+crc+sha1+sha2+sha3"))
+  else if (__builtin_cpu_supports("rdm+lse+fp+simd+crc+sha2+sha3"))
     return 2;
-  else if (__builtin_cpu_supports("aes+pmull+fp16+dit+dpb+dpb2+jscvt"))
+  else if (__builtin_cpu_supports("aes+fp16+dit+dpb+dpb2+jscvt"))
     return 3;
   else if (__builtin_cpu_supports("fcma+rcpc+rcpc2+rcpc3+frintts"))
     return 4;
   else if (__builtin_cpu_supports("i8mm+bf16+sve"))
     return 5;
-  else if (__builtin_cpu_supports("sve+ebf16+i8mm+f32mm+f64mm"))
+  else if (__builtin_cpu_supports("sve+bf16+i8mm+f32mm+f64mm"))
     return 6;
-  else if (__builtin_cpu_supports("sve2+sve2-aes+sve2-pmull128"))
+  else if (__builtin_cpu_supports("sve2+sve2-aes"))
     return 7;
   else if (__builtin_cpu_supports("sve2-bitperm+sve2-sha3+sve2-sm4"))
     return 8;
   else if (__builtin_cpu_supports("sme+memtag+sb"))
     return 9;
-  else if (__builtin_cpu_supports("predres+ssbs+ssbs2+bti+ls64+ls64_v"))
+  else if (__builtin_cpu_supports("predres+ssbs+bti+ls64"))
     return 10;
-  else if (__builtin_cpu_supports("ls64_accdata+wfxt+sme-f64f64"))
+  else if (__builtin_cpu_supports("wfxt+sme-f64f64"))
     return 11;
   else if (__builtin_cpu_supports("sme-i16i64+sme2"))
     return 12;
@@ -29,16 +152,62 @@ int check_all_feature() {
     return 0;
 }
 
-// CHECK-LABEL: define dso_local i32 @neon_code() #1
+// CHECK: Function Attrs: noinline nounwind optnone
+// CHECK-LABEL: define dso_local i32 @neon_code(
+// CHECK-SAME: ) #[[ATTR1:[0-9]+]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    ret i32 1
+//
 int __attribute__((target("simd"))) neon_code() { return 1; }
 
-// CHECK-LABEL: define dso_local i32 @sve_code() #2
+// CHECK: Function Attrs: noinline nounwind optnone
+// CHECK-LABEL: define dso_local i32 @sve_code(
+// CHECK-SAME: ) #[[ATTR2:[0-9]+]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    ret i32 2
+//
 int __attribute__((target("sve"))) sve_code() { return 2; }
 
-// CHECK-LABEL: define dso_local i32 @code() #0
+// CHECK: Function Attrs: noinline nounwind optnone
+// CHECK-LABEL: define dso_local i32 @code(
+// CHECK-SAME: ) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    ret i32 3
+//
 int code() { return 3; }
 
-// CHECK-LABEL: define dso_local i32 @test_versions() #0
+// CHECK: Function Attrs: noinline nounwind optnone
+// CHECK-LABEL: define dso_local i32 @test_versions(
+// CHECK-SAME: ) #[[ATTR0]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
+// CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 1073807616
+// CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1073807616
+// CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
+// CHECK-NEXT:    br i1 [[TMP3]], label %[[IF_THEN:.*]], label %[[IF_ELSE:.*]]
+// CHECK:       [[IF_THEN]]:
+// CHECK-NEXT:    [[CALL:%.*]] = call i32 @sve_code()
+// CHECK-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 4
+// CHECK-NEXT:    br label %[[RETURN:.*]]
+// CHECK:       [[IF_ELSE]]:
+// CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
+// CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 768
+// CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 768
+// CHECK-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
+// CHECK-NEXT:    br i1 [[TMP7]], label %[[IF_THEN1:.*]], label 
%[[IF_ELSE3:.*]]
+// CHECK:       [[IF_THEN1]]:
+// CHECK-NEXT:    [[CALL2:%.*]] = call i32 @neon_code()
+// CHECK-NEXT:    store i32 [[CALL2]], ptr [[RETVAL]], align 4
+// CHECK-NEXT:    br label %[[RETURN]]
+// CHECK:       [[IF_ELSE3]]:
+// CHECK-NEXT:    [[CALL4:%.*]] = call i32 @code()
+// CHECK-NEXT:    store i32 [[CALL4]], ptr [[RETVAL]], align 4
+// CHECK-NEXT:    br label %[[RETURN]]
+// CHECK:       [[RETURN]]:
+// CHECK-NEXT:    [[TMP8:%.*]] = load i32, ptr [[RETVAL]], align 4
+// CHECK-NEXT:    ret i32 [[TMP8]]
+//
 int test_versions() {
   if (__builtin_cpu_supports("sve"))
     return sve_code();
@@ -47,6 +216,12 @@ int test_versions() {
   else
     return code();
 }
-// CHECK: attributes #0 = { noinline nounwind optnone 
"no-trapping-math"="true" "stack-protector-buffer-size"="8" }
-// CHECK: attributes #1 = { noinline nounwind optnone 
"no-trapping-math"="true" "stack-protector-buffer-size"="8" 
"target-features"="+fp-armv8,+neon" }
-// CHECK: attributes #2 = { noinline nounwind optnone 
"no-trapping-math"="true" "stack-protector-buffer-size"="8" 
"target-features"="+fp-armv8,+fullfp16,+sve" }
+
+//.
+// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone 
"no-trapping-math"="true" "stack-protector-buffer-size"="8" }
+// CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone 
"no-trapping-math"="true" "stack-protector-buffer-size"="8" 
"target-features"="+fp-armv8,+neon" }
+// CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone 
"no-trapping-math"="true" "stack-protector-buffer-size"="8" 
"target-features"="+fp-armv8,+fullfp16,+sve" }
+//.
+// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
+// CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
+//.


        
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