================
@@ -2121,14 +1863,21 @@ def LHARXL : XForm_1_memOp<31, 116, (outs gprc:$RST),
(ins (memrr $RA, $RB):$ad
def LWARXL : XForm_1_memOp<31, 20, (outs gprc:$RST), (ins (memrr $RA,
$RB):$addr),
"lwarx $RST, $addr, 1", IIC_LdStLWARX, []>, isRecordForm;
+}
// The atomic instructions use the destination register as well as the next one
// or two registers in order (modulo 31).
-let hasExtraSrcRegAllocReq = 1 in
-def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$RST), (ins gprc:$RA, u5imm:$RB),
+let hasExtraSrcRegAllocReq = 1, mayLoad = 1, mayStore = 1 in
+def LWAT : X_RD5_RS5_IM5<31, 582, (outs g8prc:$RST), (ins g8prc:$RSTi,
ptr_rc_nor0:$RA, u5imm:$RB),
----------------
lei137 wrote:
This instruction is now changed to take g8prc but technically this is also
valid for gprc. Maybe a codegen only version should be generated for this in
the 64bit Instr td file?
https://github.com/llvm/llvm-project/pull/168746
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