================
@@ -3936,6 +3936,23 @@ MachineBasicBlock::iterator
RISCVInstrInfo::insertOutlinedCall(
return It;
}
+void RISCVInstrInfo::buildClearRegister(Register Reg, MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator Iter,
+ DebugLoc &DL,
+ bool AllowSideEffects) const {
+
+ const MachineFunction &MF = *MBB.getParent();
+ const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>();
----------------
lenary wrote:
This should already be available as the `STI` member.
https://github.com/llvm/llvm-project/pull/194883
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