diff -Nru libpfm4-4.11.1+git8-gc96ebc0/README libpfm4-4.11.1+git32-gd0b85fb/README
--- libpfm4-4.11.1+git8-gc96ebc0/README	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/README	2021-06-09 09:24:16.000000000 +0200
@@ -41,6 +41,7 @@
 		AMD64 Fam16h (Jaguar)
 		AMD64 Fam17h (Zen1)
 		AMD64 Fam17h (Zen2)
+		AMD64 Fam19h (Zen3) (core and L3)
 
 	- For Intel X86: 
 		Intel P6 (Pentium II, Pentium Pro, Pentium III, Pentium M)
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/debian/changelog libpfm4-4.11.1+git32-gd0b85fb/debian/changelog
--- libpfm4-4.11.1+git8-gc96ebc0/debian/changelog	2021-01-07 16:07:20.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/debian/changelog	2021-06-16 16:32:36.000000000 +0200
@@ -1,3 +1,12 @@
+libpfm4 (4.11.1+git32-gd0b85fb-1) unstable; urgency=medium
+
+  * New upstream GIT snapshot.
+    - Add/improve support for current CPUs: AMD Zen2, Zen3; Intel IcelakeX,
+      Tigerlake, Rocketlake; ARM A64FX, Neoverse.
+    - Fix event encoding issues.
+
+ -- Andreas Beckmann <anbe@debian.org>  Wed, 16 Jun 2021 16:32:36 +0200
+
 libpfm4 (4.11.1+git8-gc96ebc0-1) unstable; urgency=medium
 
   * New upstream GIT snapshot.
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/docs/Makefile libpfm4-4.11.1+git32-gd0b85fb/docs/Makefile
--- libpfm4-4.11.1+git8-gc96ebc0/docs/Makefile	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/docs/Makefile	2021-06-09 09:24:16.000000000 +0200
@@ -41,6 +41,8 @@
 	 libpfm_amd64_fam16h.3	\
 	 libpfm_amd64_fam17h.3	\
 	 libpfm_amd64_fam17h_zen2.3 \
+	 libpfm_amd64_fam19h_zen3.3 \
+	 libpfm_amd64_fam19h_zen3_l3.3 \
 	 libpfm_intel_atom.3	\
 	 libpfm_intel_nhm.3	\
 	 libpfm_intel_nhm_unc.3 \
@@ -57,6 +59,7 @@
 	 libpfm_intel_tmt.3	\
 	 libpfm_intel_skl.3	\
 	 libpfm_intel_icl.3	\
+	 libpfm_intel_icx.3	\
 	 libpfm_intel_glm.3	\
 	 libpfm_intel_knl.3	\
 	 libpfm_intel_knm.3	\
@@ -123,7 +126,6 @@
 	    libpfm_arm_ac8.3 \
 	    libpfm_arm_ac9.3 \
 	    libpfm_arm_qcom_krait.3 \
-	    libpfm_arm_a64fx.3 \
 	    libpfm_arm_neoverse_n1.3
 endif
 
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/docs/man3/libpfm_amd64_fam19h_zen3.3 libpfm4-4.11.1+git32-gd0b85fb/docs/man3/libpfm_amd64_fam19h_zen3.3
--- libpfm4-4.11.1+git8-gc96ebc0/docs/man3/libpfm_amd64_fam19h_zen3.3	1970-01-01 01:00:00.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/docs/man3/libpfm_amd64_fam19h_zen3.3	2021-06-09 09:24:16.000000000 +0200
@@ -0,0 +1,49 @@
+.TH LIBPFM 3  "February, 2021" "" "Linux Programmer's Manual"
+.SH NAME
+libpfm_amd64_fam19h_zen3 - support for AMD64 Family 19h processors
+.SH SYNOPSIS
+.nf
+.B #include <perfmon/pfmlib.h>
+.sp
+.B PMU name: amd64_fam19h_zen3
+.B PMU desc: AMD64 Fam19h Zen3
+.sp
+.SH DESCRIPTION
+The library supports AMD Family 19h processors Zen3 core PMU in both 32 and 64-bit modes.
+
+.SH MODIFIERS
+The following modifiers are supported on AMD64 Family 19h Zen3 core PMU:
+.TP
+.B u
+Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR.
+This is a boolean modifier.
+.TP
+.B k
+Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR.
+This is a boolean modifier.
+.TP
+.B h
+Measure at while executing in host mode (when using virtualization). This corresponds to \fBPFM_PLMH\fR.
+This modifier is available starting with Fam10h. This is a boolean modifier.
+.TP
+.B g
+Measure at while executing in guest mode (when using virtualization). This modifier is available
+starting with Fam10h. This is a boolean modifier.
+.TP
+.B i
+Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR
+occurring. This is a boolean modifier
+.TP
+.B e
+Enable edge detection, i.e., count only when there is a state transition. This is a boolean modifier.
+.TP
+.B c
+Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles
+in which the number of occurrences of the event is greater or equal to the threshold. This is an integer
+modifier with values in the range [0:255].
+
+.SH AUTHORS
+.nf
+Swarup Sahoo
+.if
+.PP
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/docs/man3/libpfm_amd64_fam19h_zen3_l3.3 libpfm4-4.11.1+git32-gd0b85fb/docs/man3/libpfm_amd64_fam19h_zen3_l3.3
--- libpfm4-4.11.1+git8-gc96ebc0/docs/man3/libpfm_amd64_fam19h_zen3_l3.3	1970-01-01 01:00:00.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/docs/man3/libpfm_amd64_fam19h_zen3_l3.3	2021-06-09 09:24:16.000000000 +0200
@@ -0,0 +1,19 @@
+.TH LIBPFM 3  "March, 2021" "" "Linux Programmer's Manual"
+.SH NAME
+libpfm_amd64_fam19h_zen3_l3 - support for AMD64 Family 19h L3 PMU
+.SH SYNOPSIS
+.nf
+.B #include <perfmon/pfmlib.h>
+.sp
+.B PMU name: amd64_fam19h_zen3_l3
+.B PMU desc: AMD64 Fam19h Zen3 L3
+.sp
+.SH DESCRIPTION
+The library supports AMD Family 19h processors Zen3 L3 PMU in both 32 and 64-bit modes.
+
+At this point, there is no modifier supported.
+.SH AUTHORS
+.nf
+Stephane Eranian
+.if
+.PP
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/docs/man3/libpfm_arm_a64fx.3 libpfm4-4.11.1+git32-gd0b85fb/docs/man3/libpfm_arm_a64fx.3
--- libpfm4-4.11.1+git8-gc96ebc0/docs/man3/libpfm_arm_a64fx.3	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/docs/man3/libpfm_arm_a64fx.3	2021-06-09 09:24:16.000000000 +0200
@@ -11,8 +11,8 @@
 .SH DESCRIPTION
 The library supports the Fujitsu A64FX core PMU.
 
-This PMU supports 6 counters and privilege levels filtering.
-It can operate in both 32 and 64 bit modes.
+This PMU supports 8 counters and privilege levels filtering.
+It can operate in 64 bit mode only.
 
 .SH MODIFIERS
 The following modifiers are supported on Fujitsu A64FX:
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/docs/man3/libpfm_intel_icl.3 libpfm4-4.11.1+git32-gd0b85fb/docs/man3/libpfm_intel_icl.3
--- libpfm4-4.11.1+git8-gc96ebc0/docs/man3/libpfm_intel_icl.3	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/docs/man3/libpfm_intel_icl.3	2021-06-09 09:24:16.000000000 +0200
@@ -1,4 +1,4 @@
-.TH LIBPFM 3  "August, 2015" "" "Linux Programmer's Manual"
+.TH LIBPFM 3  "August, 2019" "" "Linux Programmer's Manual"
 .SH NAME
 libpfm_intel_icl - support for Intel IceLake core PMU
 .SH SYNOPSIS
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/docs/man3/libpfm_intel_icx.3 libpfm4-4.11.1+git32-gd0b85fb/docs/man3/libpfm_intel_icx.3
--- libpfm4-4.11.1+git8-gc96ebc0/docs/man3/libpfm_intel_icx.3	1970-01-01 01:00:00.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/docs/man3/libpfm_intel_icx.3	2021-06-09 09:24:16.000000000 +0200
@@ -0,0 +1,84 @@
+.TH LIBPFM 3  "May, 2021" "" "Linux Programmer's Manual"
+.SH NAME
+libpfm_intel_icx - support for Intel IceLakeX core PMU
+.SH SYNOPSIS
+.nf
+.B #include <perfmon/pfmlib.h>
+.sp
+.B PMU name: icx
+.B PMU desc: Intel IceLakeX
+.sp
+.SH DESCRIPTION
+The library supports the Intel IceLakeX core PMU. It should be noted that
+this PMU model only covers each core's PMU and not the socket level
+PMU.
+
+On IceLake, the number of generic counters depends on the Hyperthreading (HT) mode.
+
+The \fBpfm_get_pmu_info()\fR function returns the maximum number
+of generic counters in \fBnum_cntrs\fr.
+
+.SH MODIFIERS
+The following modifiers are supported on Intel IceLakeX processors:
+.TP
+.B u
+Measure at user level which includes privilege levels 1, 2, 3. This corresponds to \fBPFM_PLM3\fR.
+This is a boolean modifier.
+.TP
+.B k
+Measure at kernel level which includes privilege level 0. This corresponds to \fBPFM_PLM0\fR.
+This is a boolean modifier.
+.TP
+.B i
+Invert the meaning of the event. The counter will now count cycles in which the event is \fBnot\fR
+occurring. This is a boolean modifier
+.TP
+.B e
+Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event
+to at least one occurrence. This modifier must be combined with a counter mask modifier (m) with a value greater or equal to one.
+This is a boolean modifier.
+.TP
+.B c
+Set the counter mask value. The mask acts as a threshold. The counter will count the number of cycles
+in which the number of occurrences of the event is greater or equal to the threshold. This is an integer
+modifier with values in the range [0:255].
+.TP
+.B ldlat
+Pass a latency threshold to the MEM_TRANS_RETIRED:LOAD_LATENCY event.
+This is an integer attribute that must be in the range [3:65535]. It is required
+for this event.  Note that the event must be used with precise sampling (PEBS).
+.TP
+.B intx
+Monitor the event only when executing inside a transactional memory region (in tx). Event
+does not count otherwise. This is a boolean modifiers. Default value is 0.
+.TP
+.B intxcp
+Do not count occurrences of the event when they are inside an aborted transactional memory
+region. This is a boolean modifier. Default value is 0.
+.TP
+.B fe_thres
+This modifier is for the FRONTEND_RETIRED event only. It defines the period in core cycles after which the IDQ_*_BUBBLES umask
+counts. It acts as a threshold, i.e., at least a period of N core cycles where the frontend did not deliver X uops. It can only
+be used with the IDQ_*_BUBBLES umasks. If not specified, the default threshold value is 1 cycle. the valid values are in [1-4095].
+
+.SH OFFCORE_RESPONSE events
+Intel IceLakeX supports two encodings for offcore_response events. In the library, these are called OFFCORE_RESPONSE_0 and OFFCORE_RESPONSE_1.
+
+Those events need special treatment in the performance monitoring infrastructure
+because each event uses an extra register to store some settings. Thus, in
+case multiple offcore_response events are monitored simultaneously, the operating system needs
+to manage the sharing of that extra register.
+
+The offcore_response events are exposed as a normal events by the library. The extra
+settings are exposed as regular umasks. The library takes care of encoding the
+events according to the underlying kernel interface.
+
+On Intel IceLakeX unlike older processors, the event is treated as a regular event with a flat set of umasks to choose from.
+It is not possible to combine the various requests, supplier, snoop bits anymore. Therefore the
+library offers the list of validated combinations as per Intel's official event list.
+
+.SH AUTHORS
+.nf
+Stephane Eranian <eranian@gmail.com>
+.if
+.PP
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/docs/man3/pfm_get_os_event_encoding.3 libpfm4-4.11.1+git32-gd0b85fb/docs/man3/pfm_get_os_event_encoding.3
--- libpfm4-4.11.1+git8-gc96ebc0/docs/man3/pfm_get_os_event_encoding.3	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/docs/man3/pfm_get_os_event_encoding.3	2021-06-09 09:24:16.000000000 +0200
@@ -23,7 +23,7 @@
 .TP
 .B PFM_OS_NONE
 This value causes the event to be encoded purely as specified by the PMU hardware. The \fBarg\fR
-argument must be a pointer to a \fBpfm_raw_pmu_encode_arg_t\fR structure which is defined as follows:
+argument must be a pointer to a \fBpfm_pmu_encode_arg_t\fR structure which is defined as follows:
 
 .nf
 typedef struct {
@@ -88,7 +88,7 @@
 The \fBarg\fR must be a pointer to a \fBpfm_perf_encode_arg_t\fR structure. The PFM_OS_PERF_EVENT layer
 provides the modifiers exported by the underlying PMU hardware, some of which may actually be overridden
 by the perf_event interface, such as the monitoring privilege levels. The \fBPFM_OS_PERF_EVENT_EXT\fR extends
-\fBPFM_OS_EVENT\fR to add modifiers controlled only by the perf_event interface, such as sampling period (\fBperiod\fR),
+\fBPFM_OS_PERF_EVENT\fR to add modifiers controlled only by the perf_event interface, such as sampling period (\fBperiod\fR),
 frequency (\fBfreq\fR) and exclusive resource access (\fBexcl\fR).
 
 .nf
@@ -140,23 +140,23 @@
 #include <perfmon/pfmlib.h>
 int main(int argc, char **argv)
 {
-   pfm_raw_pmu_encode_t raw;
+   pfm_pmu_encode_t arg;
    int ret;
 
    ret = pfm_initialize();
    if (ret != PFMLIB_SUCCESS)
       errx(1, "cannot initialize library %s", pfm_strerror(ret));
 
-   memset(&raw, 0, sizeof(raw));
+   memset(&arg, 0, sizeof(arg));
 
-   ret = pfm_get_os_event_encoding("RETIRED_INSTRUCTIONS", PFM_PLM3, PFM_OS_NONE, &raw);
+   ret = pfm_get_os_event_encoding("RETIRED_INSTRUCTIONS", PFM_PLM3, PFM_OS_NONE, &arg);
    if (ret != PFM_SUCCESS)
       err(1", cannot get encoding %s", pfm_strerror(ret));
 
-   for(i=0; i < raw.count; i++)
-      printf("count[%d]=0x%"PRIx64"\\n", i, raw.codes[i]);
+   for(i=0; i < arg.count; i++)
+      printf("count[%d]=0x%"PRIx64"\\n", i, arg.codes[i]);
 
-   free(raw.codes);
+   free(arg.codes);
    return 0;
 }
 .fi
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/include/perfmon/perf_event.h libpfm4-4.11.1+git32-gd0b85fb/include/perfmon/perf_event.h
--- libpfm4-4.11.1+git8-gc96ebc0/include/perfmon/perf_event.h	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/include/perfmon/perf_event.h	2021-06-09 09:24:16.000000000 +0200
@@ -115,6 +115,7 @@
 	PERF_COUNT_SW_EMULATION_FAULTS		= 8,
 	PERF_COUNT_SW_DUMMY			= 9,
 	PERF_COUNT_SW_BPF_OUTPUT		= 10,
+	PERF_COUNT_SW_CGROUP_SWITCHES           = 11,
 	PERF_COUNT_SW_MAX
 };
 
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/include/perfmon/pfmlib.h libpfm4-4.11.1+git32-gd0b85fb/include/perfmon/pfmlib.h
--- libpfm4-4.11.1+git8-gc96ebc0/include/perfmon/pfmlib.h	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/include/perfmon/pfmlib.h	2021-06-09 09:24:16.000000000 +0200
@@ -562,6 +562,13 @@
 
 	PFM_PMU_ARM_A64FX,		/* Fujitsu A64FX processor */
 	PFM_PMU_ARM_N1,			/* ARM Neoverse N1 */
+
+	PFM_PMU_AMD64_FAM19H_ZEN3,	/* AMD AMD64 Fam19h Zen3 */
+	PFM_PMU_AMD64_RAPL,		/* AMD64 RAPL */
+	PFM_PMU_AMD64_FAM19H_ZEN3_L3,	/* AMD64 Fam17h Zen3 L3 */
+
+	PFM_PMU_INTEL_ICX,		/* Intel IceLakeX */
+
 	/* MUST ADD NEW PMU MODELS HERE */
 
 	PFM_PMU_MAX			/* end marker */
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/lib/Makefile libpfm4-4.11.1+git32-gd0b85fb/lib/Makefile
--- libpfm4-4.11.1+git8-gc96ebc0/lib/Makefile	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/lib/Makefile	2021-06-09 09:24:16.000000000 +0200
@@ -124,7 +124,9 @@
 	  pfmlib_amd64_k7.c pfmlib_amd64_k8.c pfmlib_amd64_fam10h.c \
 	  pfmlib_amd64_fam11h.c pfmlib_amd64_fam12h.c \
 	  pfmlib_amd64_fam14h.c pfmlib_amd64_fam15h.c \
-	  pfmlib_amd64_fam17h.c pfmlib_amd64_fam16h.c
+	  pfmlib_amd64_fam17h.c pfmlib_amd64_fam16h.c \
+	  pfmlib_amd64_fam19h.c pfmlib_amd64_rapl.c \
+	  pfmlib_amd64_fam19h_l3.c
 
 CFLAGS += -DCONFIG_PFMLIB_ARCH_X86
 
@@ -252,6 +254,8 @@
 	events/amd64_events_fam15h.h	\
 	events/amd64_events_fam17h_zen1.h \
 	events/amd64_events_fam17h_zen2.h \
+	events/amd64_events_fam19h_zen3.h \
+	events/amd64_events_fam19h_zen3_l3.h \
 	events/amd64_events_fam16h.h	\
 	events/intel_p6_events.h	\
 	events/intel_netburst_events.h	\
@@ -371,6 +375,7 @@
         events/arm_xgene_events.h		\
 	events/arm_cavium_tx2_events.h		\
 	events/arm_marvell_tx2_unc_events.h	\
+	events/arm_fujitsu_a64fx_events.h	\
 	events/arm_neoverse_n1_events.h
 
 INCDEP=$(INC_COMMON) $(INCARCH)
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/lib/events/amd64_events_fam19h_zen3.h libpfm4-4.11.1+git32-gd0b85fb/lib/events/amd64_events_fam19h_zen3.h
--- libpfm4-4.11.1+git8-gc96ebc0/lib/events/amd64_events_fam19h_zen3.h	1970-01-01 01:00:00.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/lib/events/amd64_events_fam19h_zen3.h	2021-06-09 09:24:16.000000000 +0200
@@ -0,0 +1,999 @@
+/*
+ * Contributed by Swarup Sahoo
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
+ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
+ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * This file is part of libpfm, a performance monitoring support library for
+ * applications on Linux.
+ *
+ * PMU: amd64_fam19h_zen3 (AMD64 Fam19h Zen3)
+ */
+
+static const amd64_umask_t amd64_fam19h_zen3_retired_sse_avx_flops[]={
+  { .uname  = "ADD_SUB_FLOPS",
+    .udesc  = "Addition/subtraction FLOPS",
+    .ucode  = 0x1,
+  },
+  { .uname  = "MULT_FLOPS",
+    .udesc  = "Multiplication FLOPS",
+    .ucode  = 0x2,
+  },
+  { .uname  = "DIV_FLOPS",
+    .udesc  = "Division/Square-root FLOPS",
+    .ucode  = 0x4,
+  },
+  { .uname  = "MAC_FLOPS",
+    .udesc  = "Multiply-Accumulate flops. Each MAC operation is counted as 2 FLOPS",
+    .ucode  = 0x8,
+  },
+  { .uname  = "ANY",
+    .udesc  = "Double precision add/subtract flops",
+    .ucode  = 0xf,
+    .uflags = AMD64_FL_DFL | AMD64_FL_NCOMBO,
+  },
+};
+
+static const amd64_umask_t amd64_fam19h_zen3_retired_serializing_ops[]={
+  { .uname  = "X87_CTRL_RET",
+    .udesc  = "x87 control word mispredict traps due to mispredction in RC or PC, or changes in Exception Mask bits",
+    .ucode  = 0x1,
+  },
+  { .uname  = "X87_BOT_RET",
+    .udesc  = "x87 bottom-executing ops retired",
+    .ucode  = 0x2,
+  },
+  { .uname  = "SSE_CTRL_RET",
+    .udesc  = "SSE/AVX control word mispredict traps",
+    .ucode  = 0x4,
+  },
+  { .uname  = "SSE_BOT_RET",
+    .udesc  = "SSE/AVX bottom-executing ops retired",
+    .ucode  = 0x8,
+  },
+};
+
+static const amd64_umask_t amd64_fam19h_zen3_fp_dispatch_faults[]={
+  { .uname  = "X87_FILL_FAULT",
+    .udesc  = "x87 fill faults",
+    .ucode  = 0x1,
+  },
+  { .uname  = "XMM_FILL_FAULT",
+    .udesc  = "XMM fill faults",
+    .ucode  = 0x2,
+  },
+  { .uname  = "YMM_FILL_FAULT",
+    .udesc  = "YMM fill faults",
+    .ucode  = 0x4,
+  },
+  { .uname  = "YMM_SPILL_FAULT",
+    .udesc  = "YMM spill faults",
+    .ucode  = 0x8,
+  },
+  { .uname  = "ANY",
+    .udesc  = "Any FP dispatch faults",
+    .ucode  = 0xf,
+    .uflags = AMD64_FL_DFL | AMD64_FL_NCOMBO,
+  },
+};
+
+static const amd64_umask_t amd64_fam19h_zen3_bad_status_2[]={
+  { .uname  = "STLI_OTHER",
+    .udesc  = "Store-to-load conflicts. A load was unable to complete due to a non-forwardable conflict with an older store",
+    .ucode  = 0x2,
+    .uflags = AMD64_FL_DFL,
+  },
+};
+
+static const amd64_umask_t amd64_fam19h_zen3_retired_lock_instructions[]={
+  { .uname  = "BUS_LOCK",
+    .udesc  = "Number of bus locks",
+    .ucode  = 0x1,
+    .uflags = AMD64_FL_DFL,
+  },
+};
+
+static const amd64_umask_t amd64_fam19h_zen3_ls_dispatch[]={
+  { .uname  = "LD_ST_DISPATCH",
+    .udesc  = "Dispatched op that performs a load from and store to the same memory address",
+    .ucode  = 0x4,
+  },
+  { .uname  = "STORE_DISPATCH",
+    .udesc  = "Store ops dispatched",
+    .ucode  = 0x2,
+  },
+  { .uname  = "LD_DISPATCH",
+    .udesc  = "Load ops dispatched",
+    .ucode  = 0x1,
+  },
+};
+
+static const amd64_umask_t amd64_fam19h_zen3_store_commit_cancels_2[]={
+  { .uname  = "WCB_FULL",
+    .udesc  = "Non cacheable store and the non-cacheable commit buffer is full",
+    .ucode  = 0x1,
+    .uflags = AMD64_FL_DFL,
+  },
+};
+
+static const amd64_umask_t amd64_fam19h_zen3_mab_allocation_by_type[]={
+  { .uname  = "LS",
+    .udesc  = "Load store allocations",
+    .ucode  = 0x3f,
+    .uflags = AMD64_FL_NCOMBO,
+  },
+  { .uname  = "HW_PF",
+    .udesc  = "Hardware prefetcher allocations",
+    .ucode  = 0x40,
+    .uflags = AMD64_FL_NCOMBO,
+  },
+  { .uname  = "ALL",
+    .udesc  = "All allocations",
+    .ucode  = 0x7f,
+    .uflags = AMD64_FL_NCOMBO,
+  },
+};
+
+static const amd64_umask_t amd64_fam19h_zen3_software_prefetch_data_cache_fills[]={
+  { .uname  = "LCL_L2",
+    .udesc  = "Fill from local L2 to the core",
+    .ucode  = 0x1,
+  },
+  { .uname  = "INT_CACHE",
+    .udesc  = "Fill from L3 or different L2 in same CCX",
+    .ucode  = 0x2,
+  },
+  { .uname  = "EXT_CACHE_LCL",
+    .udesc  = "Fill from cache of different CCX in same node",
+    .ucode  = 0x4,
+  },
+  { .uname  = "MEM_IO_LCL",
+    .udesc  = "Fill from DRAM or IO connected in same node",
+    .ucode  = 0x8,
+  },
+  { .uname  = "EXT_CACHE_RMT",
+    .udesc  = "Fill from CCX cache in different node",
+    .ucode  = 0x10,
+  },
+  { .uname  = "MEM_IO_RMT",
+    .udesc  = "Fill from DRAM or IO connected in different node",
+    .ucode  = 0x40,
+  },
+};
+
+static const amd64_umask_t amd64_fam19h_zen3_l1_dtlb_miss[]={
+  { .uname  = "TLB_RELOAD_1G_L2_MISS",
+    .udesc  = "Data TLB reload to a 1GB page that missed in the L2 TLB",
+    .ucode  = 0x80,
+  },
+  { .uname  = "TLB_RELOAD_2M_L2_MISS",
+    .udesc  = "Data TLB reload to a 2MB page that missed in the L2 TLB",
+    .ucode  = 0x40,
+  },
+  { .uname  = "TLB_RELOAD_COALESCED_PAGE_MISS",
+    .udesc  = "Data TLB reload to a coalesced page that also missed in the L2 TLB",
+    .ucode  = 0x20,
+  },
+  { .uname  = "TLB_RELOAD_4K_L2_MISS",
+    .udesc  = "Data TLB reload to a 4KB page that missed in the L2 TLB",
+    .ucode  = 0x10,
+  },
+  { .uname  = "TLB_RELOAD_1G_L2_HIT",
+    .udesc  = "Data TLB reload to a 1GB page that hit in the L2 TLB",
+    .ucode  = 0x8,
+  },
+  { .uname  = "TLB_RELOAD_2M_L2_HIT",
+    .udesc  = "Data TLB reload to a 2MB page that hit in the L2 TLB",
+    .ucode  = 0x4,
+  },
+  { .uname  = "TLB_RELOAD_COALESCED_PAGE_HIT",
+    .udesc  = "Data TLB reload to a coalesced page that hit in the L2 TLB",
+    .ucode  = 0x2,
+  },
+  { .uname  = "TLB_RELOAD_4K_L2_HIT",
+    .udesc  = "Data TLB reload to a 4KB page that hit in the L2 TLB",
+    .ucode  = 0x1,
+  },
+};
+
+static const amd64_umask_t amd64_fam19h_zen3_misaligned_loads[]={
+  { .uname  = "MA4K",
+    .udesc  = "The number of 4KB misaligned (page crossing) loads",
+    .ucode  = 0x2,
+  },
+  { .uname  = "MA64",
+    .udesc  = "The number of 64B misaligned (cacheline crossing) loads",
+    .ucode  = 0x1,
+  },
+};
+
+static const amd64_umask_t amd64_fam19h_zen3_prefetch_instructions_dispatched[]={
+  { .uname  = "PREFETCH_T0_T1_T2",
+    .udesc  = "Number of prefetcht0, perfetcht1, prefetcht2 instructions dispatched",
+    .ucode  = 0x1,
+  },
+  { .uname  = "PREFETCHW",
+    .udesc  = "Number of prefetchtw instructions dispatched",
+    .ucode  = 0x2,
+  },
+  { .uname  = "PREFETCHNTA",
+    .udesc  = "Number of prefetchtnta instructions dispatched",
+    .ucode  = 0x4,
+  },
+  { .uname  = "ANY",
+    .udesc  = "Any prefetch",
+    .ucode  = 0x7,
+    .uflags = AMD64_FL_DFL | AMD64_FL_NCOMBO,
+  },
+};
+
+static const amd64_umask_t amd64_fam19h_zen3_ineffective_software_prefetch[]={
+  { .uname  = "MAB_MCH_CNT",
+    .udesc  = "Software prefetch instructions saw a match on an already allocated miss request buffer",
+    .ucode  = 0x2,
+  },
+  { .uname  = "DATA_PIPE_SW_PF_DC_HIT",
+    .udesc  = "Software Prefetch instruction saw a DC hit",
+    .ucode  = 0x1,
+  },
+};
+
+static const amd64_umask_t amd64_fam19h_zen3_tlb_flushes[]={
+  { .uname  = "ALL",
+    .udesc  = "Any TLB flush",
+    .ucode  = 0xff,
+    .uflags = AMD64_FL_DFL,
+  },
+};
+
+static const amd64_umask_t amd64_fam19h_zen3_l1_itlb_miss_l2_itlb_miss[]={
+  { .uname  = "COALESCED4K",
+    .udesc  = "Number of instruction fetches to a >4K coalesced page",
+    .ucode  = 0x8,
+  },
+  { .uname  = "IF1G",
+    .udesc  = "Number of instruction fetches to a 1GB page",
+    .ucode  = 0x4,
+  },
+  { .uname  = "IF2M",
+    .udesc  = "Number of instruction fetches to a 2MB page",
+    .ucode  = 0x2,
+  },
+  { .uname  = "IF4K",
+    .udesc  = "Number of instruction fetches to a 4KB page",
+    .ucode  = 0x1,
+  },
+};
+
+static const amd64_umask_t amd64_fam19h_zen3_itlb_fetch_hit[]={
+  { .uname  = "IF1G",
+    .udesc  = "L1 instruction fetch TLB hit a 1GB page size",
+    .ucode  = 0x4,
+  },
+  { .uname  = "IF2M",
+    .udesc  = "L1 instruction fetch TLB hit a 2MB page size",
+    .ucode  = 0x2,
+  },
+  { .uname  = "IF4K",
+    .udesc  = "L1 instruction fetch TLB hit a 4KB or 16KB page size",
+    .ucode  = 0x1,
+  },
+};
+
+static const amd64_umask_t amd64_fam19h_zen3_ic_tag_hit_miss[]={
+  { .uname  = "IC_HIT",
+    .udesc  = "Instruction cache hit",
+    .ucode  = 0x7,
+    .uflags = AMD64_FL_NCOMBO,
+  },
+  { .uname  = "IC_MISS",
+    .udesc  = "Instruction cache miss",
+    .ucode  = 0x18,
+    .uflags = AMD64_FL_NCOMBO,
+  },
+  { .uname  = "ALL_IC_ACCESS",
+    .udesc  = "All instruction cache accesses",
+    .ucode  = 0x1f,
+    .uflags = AMD64_FL_NCOMBO,
+  },
+};
+
+static const amd64_umask_t amd64_fam19h_zen3_op_cache_hit_miss[]={
+  { .uname  = "OC_HIT",
+    .udesc  = "Op cache hit",
+    .ucode  = 0x3,
+    .uflags = AMD64_FL_NCOMBO,
+  },
+  { .uname  = "OC_MISS",
+    .udesc  = "Op cache miss",
+    .ucode  = 0x4,
+    .uflags = AMD64_FL_NCOMBO,
+  },
+  { .uname  = "ALL_OC_ACCESS",
+    .udesc  = "All op cache accesses",
+    .ucode  = 0x7,
+    .uflags = AMD64_FL_NCOMBO,
+  },
+};
+
+static const amd64_umask_t amd64_fam19h_zen3_ops_source_dispatched_from_decoder[]={
+  { .uname  = "X86DECODER_DISPATCHED",
+    .udesc  = "Number of ops fetched from Instruction Cache and dispatched",
+    .ucode  = 0x1,
+  },
+  { .uname  = "OPCACHE_DISPATCHED",
+    .udesc  = "Number of ops fetched from Op Cache and dispatched",
+    .ucode  = 0x2,
+  },
+};
+
+static const amd64_umask_t amd64_fam19h_zen3_ops_type_dispatched_from_decoder[]={
+  { .uname  = "FP_DISP_IBS_MODE",
+    .udesc  = "Any FP dispatch. Count aligns with IBS count",
+    .ucode  = 0x04,
+    .uflags = AMD64_FL_NCOMBO,
+  },
+  { .uname  = "INT_DISP_IBS_MODE",
+    .udesc  = "Any Integer dispatch. Count aligns with IBS count",
+    .ucode  = 0x08,
+    .uflags = AMD64_FL_NCOMBO,
+  },
+  { .uname  = "FP_DISP_RETIRE_MODE",
+    .udesc  = "Any FP dispatch. Count aligns with RETIRED_OPS count",
+    .ucode  = 0x84,
+    .uflags = AMD64_FL_NCOMBO,
+  },
+  { .uname  = "INT_DISP_RETIRE_MODE",
+    .udesc  = "Any Integer dispatch. Count aligns with RETIRED_OPS count",
+    .ucode  = 0x88,
+    .uflags = AMD64_FL_NCOMBO,
+  },
+};
+
+static const amd64_umask_t amd64_fam19h_zen3_dispatch_resource_stall_cycles_1[]={
+  { .uname  = "INT_PHY_REG_FILE_RSRC_STALL",
+    .udesc  = "Number of cycles stalled due to integer physical register file resource stalls. Applies to all ops that have integer destination register",
+    .ucode  = 0x1,
+  },
+  { .uname  = "LOAD_QUEUE_RSRC_STALL",
+    .udesc  = "Number of cycles stalled due to load queue resource stalls. Applies to all ops with load semantics",
+    .ucode  = 0x2,
+  },
+  { .uname  = "STORE_QUEUE_RSRC_STALL",
+    .udesc  = "Number of cycles stalled due to store queue resource stalls. Applies to all ops with store semantics",
+    .ucode  = 0x4,
+  },
+  { .uname  = "TAKEN_BRANCH_BUFFER_RSRC_STALL",
+    .udesc  = "Number of cycles stalled due to taken branch buffer resource stalls",
+    .ucode  = 0x10,
+  },
+  { .uname  = "FP_REG_FILE_RSRC_STALL",
+    .udesc  = "Number of cycles stalled due to floating-point register file resource stalls. Applies to all FP ops that have a destination register",
+    .ucode  = 0x20,
+  },
+  { .uname  = "FP_SCHEDULER_RSRC_STALL",
+    .udesc  = "Number of cycles stalled due to floating-point scheduler resource stalls. Applies to ops that use the FP scheduler",
+    .ucode  = 0x40,
+  },
+  { .uname  = "FP_FLUSH_RECOVERY_STALL",
+    .udesc  = "Number of cycles stalled due to floating-point flush recovery",
+    .ucode  = 0x80,
+  },
+};
+
+static const amd64_umask_t amd64_fam19h_zen3_dispatch_resource_stall_cycles_2[]={
+  { .uname  = "INT_SCHEDULER_0_TOKEN_STALL",
+    .udesc  = "Number of cycles stalled due to no tokens available for Integer Scheduler Queue 0",
+    .ucode  = 0x1,
+  },
+  { .uname  = "INT_SCHEDULER_1_TOKEN_STALL",
+    .udesc  = "Number of cycles stalled due to no tokens available for Integer Scheduler Queue 1",
+    .ucode  = 0x2,
+  },
+  { .uname  = "INT_SCHEDULER_2_TOKEN_STALL",
+    .udesc  = "Number of cycles stalled due to no tokens available for Integer Scheduler Queue 2",
+    .ucode  = 0x4,
+  },
+  { .uname  = "INT_SCHEDULER_3_TOKEN_STALL",
+    .udesc  = "Number of cycles stalled due to no tokens available for Integer Scheduler Queue 3",
+    .ucode  = 0x8,
+  },
+  { .uname  = "RETIRE_TOKEN_STALL",
+    .udesc  = "Number of cycles stalled due to insufficient tokens available for Retire Queue",
+    .ucode  = 0x20,
+  },
+};
+
+static const amd64_umask_t amd64_fam19h_zen3_retired_mmx_fp_instructions[]={
+  { .uname  = "SSE_INSTR",
+    .udesc  = "Number of SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX)",
+    .ucode  = 0x4,
+  },
+  { .uname  = "MMX_INSTR",
+    .udesc  = "Number of MMX instructions",
+    .ucode  = 0x2,
+  },
+  { .uname  = "X87_INSTR",
+    .udesc  = "Number of x87 instructions",
+    .ucode  = 0x1,
+  },
+};
+
+static const amd64_umask_t amd64_fam19h_zen3_tagged_ibs_ops[]={
+  { .uname  = "IBS_COUNT_ROLLOVER",
+    .udesc  = "Number of times a op could not be tagged by IBS because of a previous tagged op that has not retired",
+    .ucode  = 0x4,
+  },
+  { .uname  = "IBS_TAGGED_OPS_RET",
+    .udesc  = "Number of ops tagged by IBS that retired",
+    .ucode  = 0x2,
+  },
+  { .uname  = "IBS_TAGGED_OPS",
+    .udesc  = "Number of ops tagged by IBS",
+    .ucode  = 0x1,
+  },
+};
+
+static const amd64_umask_t amd64_fam19h_zen3_requests_to_l2_group1[]={
+  { .uname  = "RD_BLK_L",
+    .udesc  = "Number of data cache reads (including software and hardware prefetches)",
+    .ucode  = 0x80,
+  },
+  { .uname  = "RD_BLK_X",
+    .udesc  = "Number of data cache stores",
+    .ucode  = 0x40,
+  },
+  { .uname  = "LS_RD_BLK_C_S",
+    .udesc  = "Number of data cache shared reads",
+    .ucode  = 0x20,
+  },
+  { .uname  = "CACHEABLE_IC_READ",
+    .udesc  = "Number of instruction cache reads",
+    .ucode  = 0x10,
+  },
+  { .uname  = "CHANGE_TO_X",
+    .udesc  = "Number of requests change to writable, check L2 for current state",
+    .ucode  = 0x8,
+  },
+  { .uname  = "PREFETCH_L2",
+    .udesc  = "TBD",
+    .ucode  = 0x4,
+  },
+  { .uname  = "L2_HW_PF",
+    .udesc  = "Number of prefetches accepted by L2 pipeline, hit or miss",
+    .ucode  = 0x2,
+  },
+};
+
+static const amd64_umask_t amd64_fam19h_zen3_core_to_l2_cacheable_request_access_status[]={
+  { .uname  = "LS_RD_BLK_C_S",
+    .udesc  = "Number of data cache shared read hitting in the L2",
+    .ucode  = 0x80,
+  },
+  { .uname  = "LS_RD_BLK_L_HIT_X",
+    .udesc  = "Number of data cache reads hitting in the L2",
+    .ucode  = 0x40,
+  },
+  { .uname  = "LS_RD_BLK_L_HIT_S",
+    .udesc  = "Number of data cache reads hitting a non-modifiable line in the L2",
+    .ucode  = 0x20,
+  },
+  { .uname  = "LS_RD_BLK_X",
+    .udesc  = "Number of data cache store or state change requests hitting in the L2",
+    .ucode  = 0x10,
+  },
+  { .uname  = "LS_RD_BLK_C",
+    .udesc  = "Number of data cache requests missing in the L2 (all types)",
+    .ucode  = 0x8,
+  },
+  { .uname  = "IC_FILL_HIT_X",
+    .udesc  = "Number of instruction cache fill requests hitting a modifiable line in the L2",
+    .ucode  = 0x4,
+  },
+  { .uname  = "IC_FILL_HIT_S",
+    .udesc  = "Number of instruction cache fill requests hitting a non-modifiable line in the L2",
+    .ucode  = 0x2,
+  },
+  { .uname  = "IC_FILL_MISS",
+    .udesc  = "Number of instruction cache fill requests missing the L2",
+    .ucode  = 0x1,
+  },
+};
+
+static const amd64_entry_t amd64_fam19h_zen3_pe[]={
+  { .name   = "RETIRED_SSE_AVX_FLOPS",
+    .desc   = "This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 and therefore requires the MergeEvent",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x3,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_retired_sse_avx_flops),
+    .umasks = amd64_fam19h_zen3_retired_sse_avx_flops,
+  },
+  { .name   = "RETIRED_SERIALIZING_OPS",
+    .desc   = "The number of serializing Ops retired",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x5,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_retired_serializing_ops),
+    .umasks = amd64_fam19h_zen3_retired_serializing_ops,
+  },
+  { .name   = "FP_DISPATCH_FAULTS",
+    .desc   = "Floating-point dispatch faults",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0xe,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_fp_dispatch_faults),
+    .umasks = amd64_fam19h_zen3_fp_dispatch_faults,
+  },
+  { .name   = "BAD_STATUS_2",
+    .desc   = "TBD",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x24,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_bad_status_2),
+    .umasks = amd64_fam19h_zen3_bad_status_2,
+  },
+  { .name   = "RETIRED_LOCK_INSTRUCTIONS",
+    .desc   = "Counts the number of retired locked instructions",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x25,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_retired_lock_instructions),
+    .umasks = amd64_fam19h_zen3_retired_lock_instructions,
+  },
+  { .name   = "RETIRED_CLFLUSH_INSTRUCTIONS",
+    .desc   = "Counts the number of retired non-speculative clflush instructions",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x26,
+    .flags   = 0,
+  },
+  { .name   = "RETIRED_CPUID_INSTRUCTIONS",
+    .desc   = "Counts the number of retired cpuid instructions",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x27,
+    .flags   = 0,
+  },
+  { .name   = "LS_DISPATCH",
+    .desc   = "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x29,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_ls_dispatch),
+    .umasks = amd64_fam19h_zen3_ls_dispatch,
+  },
+  { .name   = "SMI_RECEIVED",
+    .desc   = "Counts the number system management interrupts (SMI) received",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x2b,
+    .flags   = 0,
+  },
+  { .name   = "INTERRUPT_TAKEN",
+    .desc   = "Counts the number of interrupts taken",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x2c,
+    .flags   = 0,
+  },
+  { .name   = "STORE_TO_LOAD_FORWARD",
+    .desc   = "Number of STore to Load Forward hits",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x35,
+    .flags   = 0,
+    .ngrp    = 0,
+  },
+  { .name   = "STORE_COMMIT_CANCELS_2",
+    .desc   = "TBD",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x37,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_store_commit_cancels_2),
+    .umasks = amd64_fam19h_zen3_store_commit_cancels_2,
+  },
+  { .name   = "MAB_ALLOCATION_BY_TYPE",
+    .desc   = "Counts when a LS pipe allocates a MAB entry",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x41,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_mab_allocation_by_type),
+    .umasks = amd64_fam19h_zen3_mab_allocation_by_type,
+  },
+  { .name   = "DEMAND_DATA_CACHE_FILLS_FROM_SYSTEM",
+    .desc   = "Demand Data Cache fills by data source",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x43,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_software_prefetch_data_cache_fills),
+    .umasks = amd64_fam19h_zen3_software_prefetch_data_cache_fills, /* shared */
+  },
+  { .name   = "ANY_DATA_CACHE_FILLS_FROM_SYSTEM",
+    .desc   = "Any Data Cache fills by data source",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x44,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_software_prefetch_data_cache_fills),
+    .umasks = amd64_fam19h_zen3_software_prefetch_data_cache_fills, /* shared */
+  },
+  { .name   = "L1_DTLB_MISS",
+    .desc   = "L1 Data TLB misses",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x45,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_l1_dtlb_miss),
+    .umasks = amd64_fam19h_zen3_l1_dtlb_miss,
+  },
+  { .name   = "MISALIGNED_LOADS",
+    .desc   = "Misaligned loads retired",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x47,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_misaligned_loads),
+    .umasks = amd64_fam19h_zen3_misaligned_loads,
+  },
+  { .name   = "PREFETCH_INSTRUCTIONS_DISPATCHED",
+    .desc   = "Software Prefetch Instructions Dispatched. This is a speculative event",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x4b,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_prefetch_instructions_dispatched),
+    .umasks = amd64_fam19h_zen3_prefetch_instructions_dispatched,
+  },
+  { .name   = "INEFFECTIVE_SOFTWARE_PREFETCH",
+    .desc   = "Number of software prefetches that did not fetch data outside of the processor core",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x52,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_ineffective_software_prefetch),
+    .umasks = amd64_fam19h_zen3_ineffective_software_prefetch,
+  },
+  { .name   = "SOFTWARE_PREFETCH_DATA_CACHE_FILLS",
+    .desc   = "Number of software prefetches fills by data source",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x59,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_software_prefetch_data_cache_fills),
+    .umasks = amd64_fam19h_zen3_software_prefetch_data_cache_fills, /* shared */
+  },
+  { .name   = "HARDWARE_PREFETCH_DATA_CACHE_FILLS",
+    .desc   = "Number of hardware prefetches fills by data source",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x5a,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_software_prefetch_data_cache_fills),
+    .umasks = amd64_fam19h_zen3_software_prefetch_data_cache_fills, /* shared */
+  },
+  { .name   = "ALLOC_MAB_COUNT",
+    .desc   = "Counts the in-flight L1 data cache misses (allocated Miss Address Buffers) divided by 4 and rounded down each cycle unless used with the MergeEvent functionality. If the MergeEvent is used, it counts the exact number of outstanding L1 data cache misses",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x5f,
+    .flags   = 0,
+    .ngrp    = 0,
+  },
+  { .name   = "CYCLES_NOT_IN_HALT",
+    .desc   = "Number of core cycles not in halted state",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x76,
+    .flags   = 0,
+    .ngrp    = 0,
+  },
+  { .name   = "TLB_FLUSHES",
+    .desc   = "Number of TLB flushes",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x78,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_tlb_flushes),
+    .umasks = amd64_fam19h_zen3_tlb_flushes,
+  },
+  { .name   = "INSTRUCTION_CACHE_REFILLS_FROM_L2",
+    .desc   = "Number of 64-byte instruction cachelines that was fulfilled by the L2 cache",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x82,
+    .flags   = 0,
+    .ngrp    = 0,
+  },
+  { .name   = "INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM",
+    .desc   = "Number of 64-byte instruction cachelines fulfilled from system memory or another cache",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x83,
+    .flags   = 0,
+    .ngrp    = 0,
+  },
+  { .name   = "L1_ITLB_MISS_L2_ITLB_HIT",
+    .desc   = "Number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x84,
+    .flags   = 0,
+    .ngrp    = 0,
+  },
+  { .name   = "L1_ITLB_MISS_L2_ITLB_MISS",
+    .desc   = "The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x85,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_l1_itlb_miss_l2_itlb_miss),
+    .umasks = amd64_fam19h_zen3_l1_itlb_miss_l2_itlb_miss,
+  },
+  { .name   = "L2_BTB_CORRECTION",
+    .desc   = "Number of L2 branch prediction overrides of existing prediction. This is a speculative event",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x8b,
+    .flags   = 0,
+    .ngrp    = 0,
+  },
+  { .name   = "DYNAMIC_INDIRECT_PREDICTIONS",
+    .desc   = "Number of times a branch used the indirect predictor to make a prediction",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x8e,
+    .flags   = 0,
+    .ngrp    = 0,
+  },
+  { .name   = "DECODER_OVERRIDE_BRANCH_PRED",
+    .desc   = "Number of decoder overrides of existing branch prediction",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x91,
+    .flags   = 0,
+    .ngrp    = 0,
+  },
+  { .name   = "L1_ITLB_FETCH_HIT",
+    .desc   = "Instruction fetches that hit in the L1 ITLB",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x94,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_itlb_fetch_hit),
+    .umasks = amd64_fam19h_zen3_itlb_fetch_hit,
+  },
+  { .name   = "IC_TAG_HIT_MISS",
+    .desc   = "Counts various IC tag related hit and miss events",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x18e,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_ic_tag_hit_miss),
+    .umasks = amd64_fam19h_zen3_ic_tag_hit_miss,
+  },
+  { .name   = "OP_CACHE_HIT_MISS",
+    .desc   = "Counts op cache micro-tag hit/miss events",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x28f,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_op_cache_hit_miss),
+    .umasks = amd64_fam19h_zen3_op_cache_hit_miss,
+  },
+  { .name   = "OPS_SOURCE_DISPATCHED_FROM_DECODER",
+    .desc   = "Number of ops dispatched from the decoder classified by op source",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0xaa,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_ops_source_dispatched_from_decoder),
+    .umasks = amd64_fam19h_zen3_ops_source_dispatched_from_decoder,
+  },
+  { .name   = "OPS_TYPE_DISPATCHED_FROM_DECODER",
+    .desc   = "Number of ops dispatched from the decoder classified by op type",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0xab,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_ops_type_dispatched_from_decoder),
+    .umasks = amd64_fam19h_zen3_ops_type_dispatched_from_decoder,
+  },
+  { .name   = "DISPATCH_RESOURCE_STALL_CYCLES_1",
+    .desc   = "Number of cycles where a dispatch group is valid but does not get dispatched due to a Token Stall",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0xae,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_dispatch_resource_stall_cycles_1),
+    .umasks = amd64_fam19h_zen3_dispatch_resource_stall_cycles_1,
+  },
+  { .name   = "DISPATCH_RESOURCE_STALL_CYCLES_2",
+    .desc   = "Number of cycles where a dispatch group is valid but does not get dispatched due to a Token Stall",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0xaf,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_dispatch_resource_stall_cycles_2),
+    .umasks = amd64_fam19h_zen3_dispatch_resource_stall_cycles_2,
+  },
+  { .name   = "RETIRED_INSTRUCTIONS",
+    .desc   = "Number of instructions retired",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0xc0,
+    .flags   = 0,
+    .ngrp    = 0,
+  },
+  { .name   = "RETIRED_OPS",
+    .desc   = "Number of macro-ops retired",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0xc1,
+    .flags   = 0,
+    .ngrp    = 0,
+  },
+  { .name   = "RETIRED_BRANCH_INSTRUCTIONS",
+    .desc   = "Number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0xc2,
+    .flags   = 0,
+    .ngrp    = 0,
+  },
+  { .name   = "RETIRED_BRANCH_INSTRUCTIONS_MISPREDICTED",
+    .desc   = "Number of retired branch instructions, that were mispredicted",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0xc3,
+    .flags   = 0,
+    .ngrp    = 0,
+  },
+  { .name   = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS",
+    .desc   = "Number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interrupts",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0xc4,
+    .flags   = 0,
+    .ngrp    = 0,
+  },
+  { .name   = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED",
+    .desc   = "Number of retired taken branch instructions that were mispredicted",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0xc5,
+    .flags   = 0,
+    .ngrp    = 0,
+  },
+  { .name   = "RETIRED_FAR_CONTROL_TRANSFERS",
+    .desc   = "Number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch prediction",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0xc6,
+    .flags   = 0,
+    .ngrp    = 0,
+  },
+  { .name   = "RETIRED_NEAR_RETURNS",
+    .desc   = "Number of near return instructions (RET or RET Iw) retired",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0xc8,
+    .flags   = 0,
+    .ngrp    = 0,
+  },
+  { .name   = "RETIRED_NEAR_RETURNS_MISPREDICTED",
+    .desc   = "Number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0xc9,
+    .flags   = 0,
+    .ngrp    = 0,
+  },
+  { .name   = "RETIRED_INDIRECT_BRANCH_INSTRUCTIONS_MISPREDICTED",
+    .desc   = "Number of indirect branches retired there were not correctly predicted. Each such mispredict incurs the same penalty as a mispredicted condition branch instruction. Only EX mispredicts are counted",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0xca,
+    .flags   = 0,
+    .ngrp    = 0,
+  },
+  { .name   = "RETIRED_MMX_FP_INSTRUCTIONS",
+    .desc   = "Number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions, it is not suitable for measuring MFLOPS",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0xcb,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_retired_mmx_fp_instructions),
+    .umasks = amd64_fam19h_zen3_retired_mmx_fp_instructions,
+  },
+  { .name   = "RETIRED_INDIRECT_BRANCH_INSTRUCTIONS",
+    .desc   = "Number of indirect branches retired",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0xcc,
+    .flags   = 0,
+    .ngrp    = 0,
+  },
+  { .name   = "RETIRED_CONDITIONAL_BRANCH_INSTRUCTIONS",
+    .desc   = "Number of retired conditional branch instructions",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0xd1,
+    .flags   = 0,
+    .ngrp    = 0,
+  },
+  { .name   = "DIV_CYCLES_BUSY_COUNT",
+    .desc   = "Number of cycles when the divider is busy",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0xd3,
+    .flags   = 0,
+    .ngrp    = 0,
+  },
+  { .name   = "DIV_OP_COUNT",
+    .desc   = "Number of divide ops",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0xd4,
+    .flags   = 0,
+    .ngrp    = 0,
+  },
+  { .name   = "RETIRED_BRANCH_MISPREDICTED_DIRECTION_MISMATCH",
+    .desc   = "Number of retired conditional branch instructions that were not correctly predicted because of branch direction mismatch",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x1c7,
+    .flags   = 0,
+    .ngrp    = 0,
+  },
+  { .name   = "TAGGED_IBS_OPS",
+    .desc   = "Counts Op IBS related events",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x1cf,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_tagged_ibs_ops),
+    .umasks = amd64_fam19h_zen3_tagged_ibs_ops,
+  },
+  { .name   = "RETIRED_FUSED_INSTRUCTIONS",
+    .desc   = "Counts retired fused instructions",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x1d0,
+    .flags   = 0,
+    .ngrp    = 0,
+  },
+  { .name   = "REQUESTS_TO_L2_GROUP1",
+    .desc   = "All L2 cache requests",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x60,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_requests_to_l2_group1),
+    .umasks = amd64_fam19h_zen3_requests_to_l2_group1,
+  },
+  { .name   = "CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS",
+    .desc   = "L2 cache request outcomes. This event does not count accesses to the L2 cache by the L2 prefetcher",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x64,
+    .flags   = 0,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_core_to_l2_cacheable_request_access_status),
+    .umasks = amd64_fam19h_zen3_core_to_l2_cacheable_request_access_status,
+  },
+  { .name   = "L2_PREFETCH_HIT_L2",
+    .desc   = "Number of L2 prefetches that hit in the L2",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x70,
+    .flags   = 0,
+    .ngrp    = 0,
+  },
+  { .name   = "L2_PREFETCH_HIT_L3",
+    .desc   = "Number of L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x71,
+    .flags   = 0,
+    .ngrp    = 0,
+  },
+  { .name   = "L2_PREFETCH_MISS_L3",
+    .desc   = "Number of L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches",
+    .modmsk  = AMD64_FAM19H_ATTRS,
+    .code    = 0x72,
+    .flags   = 0,
+    .ngrp    = 0,
+  },
+};
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/lib/events/amd64_events_fam19h_zen3_l3.h libpfm4-4.11.1+git32-gd0b85fb/lib/events/amd64_events_fam19h_zen3_l3.h
--- libpfm4-4.11.1+git8-gc96ebc0/lib/events/amd64_events_fam19h_zen3_l3.h	1970-01-01 01:00:00.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/lib/events/amd64_events_fam19h_zen3_l3.h	2021-06-09 09:24:16.000000000 +0200
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2021 Google LLC
+ * Contributed by Stephane Eranian <eranian@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
+ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
+ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * This file is part of libpfm, a performance monitoring support library for
+ * applications on Linux.
+ *
+ * PMU: amd64_fam19h_zen3_l3 (AMD64 Fam19h Zen3 L3)
+ */
+
+static const amd64_umask_t amd64_fam19h_zen3_l3_requests[]={
+  { .uname  = "ALL",
+    .udesc  = "All types of requests",
+    .ucode  = 0xff,
+    .uflags = AMD64_FL_DFL,
+  },
+};
+
+static const amd64_entry_t amd64_fam19h_zen3_l3_pe[]={
+  { .name   = "UNC_L3_REQUESTS",
+    .desc   = "Number of requests to L3 cache",
+    .code    = 0x04,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_l3_requests),
+    .umasks = amd64_fam19h_zen3_l3_requests,
+  },
+  { .name   = "UNC_L3_MISS_LATENCY",
+    .desc   = "Accumulated miss latency in cycles - occupancy event",
+    .code    = 0x90,
+  },
+  { .name   = "UNC_L3_MISSES",
+    .desc   = "Number of L3 cache misses",
+    .code    = 0x9a,
+    .ngrp    = 1,
+    .numasks = LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_l3_requests),
+    .umasks = amd64_fam19h_zen3_l3_requests, /* shared */
+  },
+};
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/lib/events/arm_neoverse_n1_events.h libpfm4-4.11.1+git32-gd0b85fb/lib/events/arm_neoverse_n1_events.h
--- libpfm4-4.11.1+git8-gc96ebc0/lib/events/arm_neoverse_n1_events.h	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/lib/events/arm_neoverse_n1_events.h	2021-06-09 09:24:16.000000000 +0200
@@ -551,4 +551,24 @@
 	 .code = 0xa0,
 	 .desc = "L3 cache reads",
 	},
+	{.name = "SAMPLE_POP",
+	 .modmsk = ARMV8_ATTRS,
+	 .code = 0x4000,
+	 .desc = "Number of operations that might be sampled by SPE, whether or not the operation was sampled",
+	},
+	{.name = "SAMPLE_FEED",
+	 .modmsk = ARMV8_ATTRS,
+	 .code = 0x4001,
+	 .desc = "Number of times the SPE sample interval counter reaches zero and is reloaded",
+	},
+	{.name = "SAMPLE_FILTRATE",
+	 .modmsk = ARMV8_ATTRS,
+	 .code = 0x4002,
+	 .desc = "Number of times SPE completed sample record passes the SPE filters and is written to the buffer"
+	},
+	{.name = "SAMPLE_COLLISION",
+	 .modmsk = ARMV8_ATTRS,
+	 .code = 0x4003,
+	 .desc = "Number of times SPE has a sample record taken when the previous sampled operation has not yet completed its record"
+	},
 };
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/lib/events/intel_icl_events.h libpfm4-4.11.1+git32-gd0b85fb/lib/events/intel_icl_events.h
--- libpfm4-4.11.1+git8-gc96ebc0/lib/events/intel_icl_events.h	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/lib/events/intel_icl_events.h	2021-06-09 09:24:16.000000000 +0200
@@ -433,6 +433,39 @@
   },
 };
 
+static const intel_x86_umask_t intel_icl_mem_load_l3_miss_retired[]={
+  { .uname   = "REMOTE_PMM",
+    .udesc   = "Retired demand load instructions which missed L3 but serviced from remote IXP memory as data sources",
+    .ucode   = 0x1000ull,
+    .umodel  = PFM_PMU_INTEL_ICX,
+    .uflags  = INTEL_X86_NCOMBO | INTEL_X86_PEBS,
+  },
+  { .uname   = "REMOTE_FWD",
+    .udesc   = "Retired load instructions whose data sources was forwarded from a remote cache",
+    .ucode   = 0x0800ull,
+    .umodel  = PFM_PMU_INTEL_ICX,
+    .uflags  = INTEL_X86_NCOMBO | INTEL_X86_PEBS,
+  },
+  { .uname   = "REMOTE_HITM",
+    .udesc   = "Retired load instructions whose data sources was remote HITM",
+    .ucode   = 0x0400ull,
+    .umodel  = PFM_PMU_INTEL_ICX,
+    .uflags  = INTEL_X86_NCOMBO | INTEL_X86_PEBS,
+  },
+  { .uname   = "REMOTE_DRAM",
+    .udesc   = "Retired load instructions which data sources missed L3 but serviced from remote dram",
+    .ucode   = 0x0200ull,
+    .umodel  = PFM_PMU_INTEL_ICX,
+    .uflags  = INTEL_X86_NCOMBO | INTEL_X86_PEBS,
+  },
+  { .uname   = "LOCAL_DRAM",
+    .udesc   = "Retired load instructions which data sources missed L3 but serviced from local dram",
+    .ucode   = 0x0100ull,
+    .uflags  = INTEL_X86_NCOMBO | INTEL_X86_PEBS,
+  },
+};
+
+
 static const intel_x86_umask_t intel_icl_mem_load_l3_hit_retired[]={
   { .uname   = "XSNP_NONE",
     .udesc   = "Retired load instructions whose data sources were hits in L3 without snoops required",
@@ -492,6 +525,12 @@
     .ucode   = 0x0100ull,
     .uflags  = INTEL_X86_NCOMBO | INTEL_X86_PEBS,
   },
+  { .uname   = "LOCAL_PMM",
+    .udesc   = "Retired demand load instructions which missed L3 but serviced from local IXP memory as data sources",
+    .ucode   = 0x8000ull,
+    .umodel  = PFM_PMU_INTEL_ICX,
+    .uflags  = INTEL_X86_NCOMBO | INTEL_X86_PEBS,
+  },
 };
 
 static const intel_x86_umask_t intel_icl_mem_inst_retired[]={
@@ -1669,6 +1708,11 @@
     .uflags  = INTEL_X86_NCOMBO,
     .modhw   = _INTEL_X86_ATTR_I | _INTEL_X86_ATTR_C,
   },
+  { .uname   = "VECTOR_WIDTH_MISMATCH",
+    .udesc   = "Uops inserted at issue-stage in order to preserve upper bits of vector registers.",
+    .ucode   = 0x0200ull,
+    .uflags  = INTEL_X86_NCOMBO,
+  },
   { .uname   = "ANY",
     .udesc   = "Uops that RAT issues to RS",
     .ucode   = 0x0100ull,
@@ -1954,6 +1998,17 @@
     .numasks= LIBPFM_ARRAY_SIZE(intel_icl_mem_inst_retired),
     .umasks = intel_icl_mem_inst_retired,
   },
+  { .name   = "MEM_LOAD_L3_MISS_RETIRED",
+    .desc   = "Retired load instructions which data sources missed L3 but serviced from local dram",
+    .code   = 0x00d3,
+    .modmsk = INTEL_V5_ATTRS,
+    .cntmsk = 0xfull,
+    .ngrp   = 1,
+    .flags  = INTEL_X86_PEBS,
+    .numasks= LIBPFM_ARRAY_SIZE(intel_icl_mem_load_l3_miss_retired),
+    .umasks = intel_icl_mem_load_l3_miss_retired,
+  },
+
   { .name   = "MEM_TRANS_RETIRED",
     .desc   = "Memory transactions retired,",
     .code   = 0x00cd,
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/lib/events/intel_skl_events.h libpfm4-4.11.1+git32-gd0b85fb/lib/events/intel_skl_events.h
--- libpfm4-4.11.1+git8-gc96ebc0/lib/events/intel_skl_events.h	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/lib/events/intel_skl_events.h	2021-06-09 09:24:16.000000000 +0200
@@ -1687,7 +1687,7 @@
      .ucode  = 1ULL << (26+8),
      .grpid  = 1,
    },
-   { .uname  = "L3_MISS_MISS_REMOTE_HOP1_DRAM",
+   { .uname  = "L3_MISS_REMOTE_HOP1_DRAM",
      .udesc  = "Supplier: counts L3 misses to remote DRAM with 1 hop",
      .ucode  = 1ULL << (28+8),
      .grpid  = 1,
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/lib/events/perf_events.h libpfm4-4.11.1+git32-gd0b85fb/lib/events/perf_events.h
--- libpfm4-4.11.1+git8-gc96ebc0/lib/events/perf_events.h	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/lib/events/perf_events.h	2021-06-09 09:24:16.000000000 +0200
@@ -30,7 +30,7 @@
 	.id   = PERF_COUNT_HW_CACHE_##e,\
 	.type = PERF_TYPE_HW_CACHE,\
 	.modmsk = PERF_ATTR_HW,\
-	.umask_ovfl_idx = -1,\
+	.umask_ovfl_idx = ~0UL,\
 	.equiv = "PERF_COUNT_HW_CACHE_"#e":WRITE:ACCESS"\
        },\
        {\
@@ -39,7 +39,7 @@
 	.id   = PERF_COUNT_HW_CACHE_##e,\
 	.type = PERF_TYPE_HW_CACHE,\
 	.modmsk = PERF_ATTR_HW,\
-	.umask_ovfl_idx = -1,\
+	.umask_ovfl_idx = ~0UL,\
 	.equiv = "PERF_COUNT_HW_CACHE_"#e":WRITE:MISS"\
        }
 
@@ -50,7 +50,7 @@
 	.id   = PERF_COUNT_HW_CACHE_##e,\
 	.type = PERF_TYPE_HW_CACHE,\
 	.modmsk = PERF_ATTR_HW,\
-	.umask_ovfl_idx = -1,\
+	.umask_ovfl_idx = ~0UL,\
 	.equiv = "PERF_COUNT_HW_CACHE_"#e":PREFETCH:ACCESS"\
        },\
        {\
@@ -59,7 +59,7 @@
 	.id   = PERF_COUNT_HW_CACHE_##e,\
 	.type = PERF_TYPE_HW_CACHE,\
 	.modmsk = PERF_ATTR_HW,\
-	.umask_ovfl_idx = -1,\
+	.umask_ovfl_idx = ~0UL,\
 	.equiv = "PERF_COUNT_HW_CACHE_"#e":PREFETCH:MISS"\
        }
 
@@ -71,7 +71,7 @@
 	.id   = PERF_COUNT_HW_CACHE_##e,\
 	.type = PERF_TYPE_HW_CACHE,\
 	.modmsk = PERF_ATTR_HW,\
-	.umask_ovfl_idx = -1,\
+	.umask_ovfl_idx = ~0UL,\
 	.equiv = "PERF_COUNT_HW_CACHE_"#e":READ:ACCESS"\
        },\
        {\
@@ -80,7 +80,7 @@
 	.id   = PERF_COUNT_HW_CACHE_##e,\
 	.type = PERF_TYPE_HW_CACHE,\
 	.modmsk = PERF_ATTR_HW,\
-	.umask_ovfl_idx = -1,\
+	.umask_ovfl_idx = ~0UL,\
 	.equiv = "PERF_COUNT_HW_CACHE_"#e":READ:MISS"\
        }
 
@@ -151,6 +151,10 @@
 
         PCL_EVT_SW(PAGE_FAULTS_MAJ),
         PCL_EVT_ASW(MAJOR-FAULTS, PAGE_FAULTS_MAJ),
+
+	PCL_EVT_SW(CGROUP_SWITCHES),
+	PCL_EVT_ASW(CGROUP-SWITCHES, CGROUP_SWITCHES),
+
 	{
 	.name = "PERF_COUNT_HW_CACHE_L1D",
 	.desc = "L1 data cache",
@@ -158,7 +162,7 @@
 	.type = PERF_TYPE_HW_CACHE,
 	.numasks = 5,
 	.modmsk = PERF_ATTR_HW,
-	.umask_ovfl_idx = -1,
+	.umask_ovfl_idx = ~0UL,
 	.ngrp = 2,
 	.umasks = {
 		{ .uname = "READ",
@@ -198,7 +202,7 @@
 	.type = PERF_TYPE_HW_CACHE,
 	.numasks = 4,
 	.modmsk = PERF_ATTR_HW,
-	.umask_ovfl_idx = -1,
+	.umask_ovfl_idx = ~0UL,
 	.ngrp = 2,
 	.umasks = {
 		{ .uname = "READ",
@@ -233,7 +237,7 @@
 	.type = PERF_TYPE_HW_CACHE,
 	.numasks = 5,
 	.modmsk = PERF_ATTR_HW,
-	.umask_ovfl_idx = -1,
+	.umask_ovfl_idx = ~0UL,
 	.ngrp = 2,
 	.umasks = {
 		{ .uname = "READ",
@@ -273,7 +277,7 @@
 	.type = PERF_TYPE_HW_CACHE,
 	.numasks = 5,
 	.modmsk = PERF_ATTR_HW,
-	.umask_ovfl_idx = -1,
+	.umask_ovfl_idx = ~0UL,
 	.ngrp = 2,
 	.umasks = {
 		{ .uname = "READ",
@@ -313,7 +317,7 @@
 	.type = PERF_TYPE_HW_CACHE,
 	.numasks = 3,
 	.modmsk = PERF_ATTR_HW,
-	.umask_ovfl_idx = -1,
+	.umask_ovfl_idx = ~0UL,
 	.ngrp = 2,
 	.umasks = {
 		{ .uname = "READ",
@@ -343,7 +347,7 @@
 	.type = PERF_TYPE_HW_CACHE,
 	.numasks = 3,
 	.modmsk = PERF_ATTR_HW,
-	.umask_ovfl_idx = -1,
+	.umask_ovfl_idx = ~0UL,
 	.ngrp = 2,
 	.umasks = {
 		{ .uname = "READ",
@@ -373,7 +377,7 @@
 	.type = PERF_TYPE_HW_CACHE,
 	.numasks = 5,
 	.modmsk = PERF_ATTR_HW,
-	.umask_ovfl_idx = -1,
+	.umask_ovfl_idx = ~0UL,
 	.ngrp = 2,
 	.umasks = {
 		{ .uname = "READ",
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_amd64.c libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_amd64.c
--- libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_amd64.c	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_amd64.c	2021-06-09 09:24:16.000000000 +0200
@@ -174,16 +174,18 @@
 	} else if (cfg->family == 21) { /* family 15h */
 		rev = PFM_PMU_AMD64_FAM15H_INTERLAGOS;
 	} else if (cfg->family == 23) { /* family 17h */
-                switch (cfg->model) {
-                case 49:
+                if (cfg->model >= 48)
 			rev = PFM_PMU_AMD64_FAM17H_ZEN2;
-			break;
-                default:
+		else
                         rev = PFM_PMU_AMD64_FAM17H_ZEN1;
-                }
 	} else if (cfg->family == 22) { /* family 16h */
 		rev = PFM_PMU_AMD64_FAM16H;
-	}
+	} else if (cfg->family == 25) { /* family 19h */
+                switch (cfg->model) {
+                default:
+                        rev = PFM_PMU_AMD64_FAM19H_ZEN3;
+                }
+        }
 
         cfg->revision = rev;
 }
@@ -282,34 +284,23 @@
 {
 	pfmlib_pmu_t *pmu = this;
 
-	if (IS_FAMILY_10H(pmu) || IS_FAMILY_15H(pmu))
-		__pfm_vbprintf("[0x%"PRIx64" event_sel=0x%x umask=0x%x os=%d usr=%d en=%d int=%d inv=%d edge=%d cnt_mask=%d guest=%d host=%d] %s\n",
-			reg.val,
-			reg.sel_event_mask | (reg.sel_event_mask2 << 8),
-			reg.sel_unit_mask,
-			reg.sel_os,
-			reg.sel_usr,
-			reg.sel_en,
-			reg.sel_int,
-			reg.sel_inv,
-			reg.sel_edge,
-			reg.sel_cnt_mask,
-			reg.sel_guest,
-			reg.sel_host,
-			e->fstr);
-	else
-		__pfm_vbprintf("[0x%"PRIx64" event_sel=0x%x umask=0x%x os=%d usr=%d en=%d int=%d inv=%d edge=%d cnt_mask=%d] %s\n",
-			reg.val,
-			reg.sel_event_mask,
-			reg.sel_unit_mask,
-			reg.sel_os,
-			reg.sel_usr,
-			reg.sel_en,
-			reg.sel_int,
-			reg.sel_inv,
-			reg.sel_edge,
-			reg.sel_cnt_mask,
-			e->fstr);
+	__pfm_vbprintf("[0x%"PRIx64" event_sel=0x%x umask=0x%x os=%d usr=%d en=%d int=%d inv=%d edge=%d cnt_mask=%d",
+		reg.val,
+		reg.sel_event_mask | (reg.sel_event_mask2 << 8),
+		reg.sel_unit_mask,
+		reg.sel_os,
+		reg.sel_usr,
+		reg.sel_en,
+		reg.sel_int,
+		reg.sel_inv,
+		reg.sel_edge,
+		reg.sel_cnt_mask);
+
+	/* Fam10h or later has host/guest filterting except Fam11h */
+	if (pfm_amd64_supports_virt(pmu))
+		__pfm_vbprintf(" guest=%d host=%d", reg.sel_guest, reg.sel_host);
+
+	__pfm_vbprintf("] %s\n", e->fstr);
 }
 
 int
@@ -541,8 +532,7 @@
 			reg.sel_os = 1;
 		if (e->dfl_plm & PFM_PLM3)
 			reg.sel_usr = 1;
-		if ((IS_FAMILY_10H(this) || IS_FAMILY_15H(this))
-		     && e->dfl_plm & PFM_PLMH)
+		if (e->dfl_plm & PFM_PLMH)
 			reg.sel_host = 1;
 	}
 
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_amd64_fam11h.c libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_amd64_fam11h.c
--- libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_amd64_fam11h.c	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_amd64_fam11h.c	2021-06-09 09:24:16.000000000 +0200
@@ -57,5 +57,5 @@
 	.get_event_nattrs	= pfm_amd64_get_event_nattrs,	\
 }
 
-DEFINE_FAM11H_REV(Turion, turion, 0, PFM_PMU_AMD64_FAM11H_TURION);
+DEFINE_FAM11H_REV(Turion, turion, AMD64_FAM11H, PFM_PMU_AMD64_FAM11H_TURION);
 
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_amd64_fam12h.c libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_amd64_fam12h.c
--- libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_amd64_fam12h.c	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_amd64_fam12h.c	2021-06-09 09:24:16.000000000 +0200
@@ -57,5 +57,5 @@
 	.get_event_nattrs	= pfm_amd64_get_event_nattrs,	\
 }
 
-DEFINE_FAM12H_REV(Llano, llano, 0, PFM_PMU_AMD64_FAM12H_LLANO);
+DEFINE_FAM12H_REV(Llano, llano, AMD64_FAM12H, PFM_PMU_AMD64_FAM12H_LLANO);
 
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_amd64_fam15h.c libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_amd64_fam15h.c
--- libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_amd64_fam15h.c	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_amd64_fam15h.c	2021-06-09 09:24:16.000000000 +0200
@@ -33,7 +33,7 @@
 	.desc			= "AMD64 Fam15h Interlagos",
 	.name			= "amd64_fam15h_interlagos",
 	.pmu			= PFM_PMU_AMD64_FAM15H_INTERLAGOS,
-	.pmu_rev		= 0,
+	.pmu_rev		= AMD64_FAM15H,
 	.pme_count		= LIBPFM_ARRAY_SIZE(amd64_fam15h_pe),
 	.type			= PFM_PMU_TYPE_CORE,
 	.supported_plm		= AMD64_FAM10H_PLM,
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_amd64_fam16h.c libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_amd64_fam16h.c
--- libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_amd64_fam16h.c	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_amd64_fam16h.c	2021-06-09 09:24:16.000000000 +0200
@@ -31,7 +31,7 @@
 	.desc			= "AMD64 Fam16h Jaguar",
 	.name			= "amd64_fam16h",
 	.pmu			= PFM_PMU_AMD64_FAM16H,
-	.pmu_rev		= 0,
+	.pmu_rev		= AMD64_FAM16H,
 	.pme_count		= LIBPFM_ARRAY_SIZE(amd64_fam16h_pe),
 	.type			= PFM_PMU_TYPE_CORE,
 	.supported_plm		= AMD64_FAM10H_PLM,
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_amd64_fam17h.c libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_amd64_fam17h.c
--- libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_amd64_fam17h.c	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_amd64_fam17h.c	2021-06-09 09:24:16.000000000 +0200
@@ -54,7 +54,7 @@
 	.desc			= "AMD64 Fam17h Zen1 (deprecated - use amd_fam17h_zen1 instead)",
 	.name			= "amd64_fam17h",
 	.pmu			= PFM_PMU_AMD64_FAM17H,
-	.pmu_rev		= 0,
+	.pmu_rev		= AMD64_FAM17H,
 	.pme_count		= LIBPFM_ARRAY_SIZE(amd64_fam17h_zen1_pe),
 	.type			= PFM_PMU_TYPE_CORE,
 	.supported_plm		= AMD64_FAM10H_PLM,
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_amd64_fam19h.c libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_amd64_fam19h.c
--- libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_amd64_fam19h.c	1970-01-01 01:00:00.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_amd64_fam19h.c	2021-06-09 09:24:16.000000000 +0200
@@ -0,0 +1,56 @@
+/*
+ * pfmlib_amd64_fam19h.c : AMD64 Fam19h core PMU support
+ *
+  * Contributed by Swarup Sahoo
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
+ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
+ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+/* private headers */
+#include "pfmlib_priv.h"
+#include "pfmlib_amd64_priv.h"
+#include "events/amd64_events_fam19h_zen3.h"
+
+
+pfmlib_pmu_t amd64_fam19h_zen3_support={
+	.desc			= "AMD64 Fam19h Zen3",
+	.name			= "amd64_fam19h_zen3",
+	.pmu			= PFM_PMU_AMD64_FAM19H_ZEN3,
+	.pmu_rev		= AMD64_FAM19H,
+	.pme_count		= LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_pe),
+	.type			= PFM_PMU_TYPE_CORE,
+	.supported_plm	        = AMD64_FAM10H_PLM,
+	.num_cntrs		= 6,
+	.max_encoding	        = 1,
+	.pe		        = amd64_fam19h_zen3_pe,
+	.atdesc			= amd64_mods,
+	.flags			= PFMLIB_PMU_FL_RAW_UMASK,
+	.cpu_family		= PFM_PMU_AMD64_FAM19H_ZEN3,
+	.pmu_detect		= pfm_amd64_family_detect,
+	.get_event_encoding[PFM_OS_NONE] = pfm_amd64_get_encoding,
+	 PFMLIB_ENCODE_PERF(pfm_amd64_get_perf_encoding),
+	.get_event_first	= pfm_amd64_get_event_first,
+	.get_event_next		= pfm_amd64_get_event_next,
+	.event_is_valid		= pfm_amd64_event_is_valid,
+	.validate_table		= pfm_amd64_validate_table,
+	.get_event_info		= pfm_amd64_get_event_info,
+	.get_event_attr_info	= pfm_amd64_get_event_attr_info,
+	 PFMLIB_VALID_PERF_PATTRS(pfm_amd64_perf_validate_pattrs),
+	.get_event_nattrs	= pfm_amd64_get_event_nattrs,
+};
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_amd64_fam19h_l3.c libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_amd64_fam19h_l3.c
--- libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_amd64_fam19h_l3.c	1970-01-01 01:00:00.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_amd64_fam19h_l3.c	2021-06-09 09:24:16.000000000 +0200
@@ -0,0 +1,76 @@
+/*
+ * pfmlib_amd64_fam19h_zen3_l3.c : AMD Fam19h Zen3 L3 PMU
+ *
+ * Copyright 2021 Google LLC
+ * Contributed by Stephane Eranian <eranian@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
+ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
+ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <sys/types.h>
+#include <ctype.h>
+#include <string.h>
+#include <stdlib.h>
+#include <stdio.h>
+
+/* private headers */
+#include "pfmlib_priv.h"
+#include "pfmlib_amd64_priv.h"
+#include "events/amd64_events_fam19h_zen3_l3.h"
+
+static void
+display_l3(void *this, pfmlib_event_desc_t *e, void *val)
+{
+	pfm_amd64_reg_t *reg = val;
+
+	__pfm_vbprintf("[L3=0x%"PRIx64" event=0x%x umask=0x%x\n",
+			reg->val,
+			reg->l3.event,
+			reg->l3.umask);
+}
+
+const pfmlib_attr_desc_t l3_mods[]={
+	PFM_ATTR_NULL
+};
+
+pfmlib_pmu_t amd64_fam19h_zen3_l3_support = {
+	.desc			= "AMD64 Fam19h Zen3 L3",
+	.name			= "amd64_fam19h_zen3_l3",
+	.perf_name		= "amd_l3",
+	.pmu			= PFM_PMU_AMD64_FAM19H_ZEN3_L3,
+	.pmu_rev		= 0,
+	.pme_count		= LIBPFM_ARRAY_SIZE(amd64_fam19h_zen3_l3_pe),
+	.type			= PFM_PMU_TYPE_UNCORE,
+	.num_cntrs		= 4,
+	.max_encoding		= 1,
+	.pe			= amd64_fam19h_zen3_l3_pe,
+	.atdesc			= l3_mods,
+	.flags			= PFMLIB_PMU_FL_RAW_UMASK,
+	.cpu_family		= PFM_PMU_AMD64_FAM19H_ZEN3,
+	.pmu_detect		= pfm_amd64_family_detect,
+	.get_event_encoding[PFM_OS_NONE] = pfm_amd64_get_encoding,
+	 PFMLIB_ENCODE_PERF(pfm_amd64_get_perf_encoding),
+	.get_event_first	= pfm_amd64_get_event_first,
+	.get_event_next		= pfm_amd64_get_event_next,
+	.event_is_valid		= pfm_amd64_event_is_valid,
+	.validate_table		= pfm_amd64_validate_table,
+	.get_event_info		= pfm_amd64_get_event_info,
+	.get_event_attr_info	= pfm_amd64_get_event_attr_info,
+	 PFMLIB_VALID_PERF_PATTRS(pfm_amd64_perf_validate_pattrs),
+	.get_event_nattrs	= pfm_amd64_get_event_nattrs,
+	.display_reg		= display_l3,
+};
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_amd64_perf_event.c libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_amd64_perf_event.c
--- libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_amd64_perf_event.c	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_amd64_perf_event.c	2021-06-09 09:24:16.000000000 +0200
@@ -60,6 +60,7 @@
 pfm_amd64_get_perf_encoding(void *this, pfmlib_event_desc_t *e)
 {
 	pfmlib_pmu_t *pmu = this;
+	pfm_amd64_reg_t reg;
 	struct perf_event_attr *attr = e->os_data;
 	int ret;
 
@@ -92,7 +93,22 @@
 	}
 	DPRINT("amd64_get_perf_encoding: PMU type=%d\n", ret);
 	attr->type = ret;
-	attr->config = e->codes[0];
+
+	reg.val = e->codes[0];
+	/*
+	 * suppress the bits which are under the control of perf_events
+	 * they will be ignore by the perf tool and the kernel interface
+	 * the OS/USR bits are controlled by the attr.exclude_* fields
+	 * the EN/INT bits are controlled by the kernel
+	 */
+	reg.sel_en    = 0;
+	reg.sel_int   = 0;
+	reg.sel_os    = 0;
+	reg.sel_usr   = 0;
+	reg.sel_guest = 0;
+	reg.sel_host  = 0;
+
+	attr->config = reg.val;
 
 	return PFM_SUCCESS;
 }
@@ -130,7 +146,7 @@
 				compact = 1;
 
 			/* older processors do not support hypervisor priv level */
-			if (!IS_FAMILY_10H(pmu) && e->pattrs[i].idx == PERF_ATTR_H)
+			if (e->pattrs[i].idx == PERF_ATTR_H &&!pfm_amd64_supports_virt(pmu))
 				compact = 1;
 		}
 
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_amd64_priv.h libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_amd64_priv.h
--- libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_amd64_priv.h	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_amd64_priv.h	2021-06-09 09:24:16.000000000 +0200
@@ -52,7 +52,6 @@
  * which would not fit into the 8 bits reserved
  * in amd64_entry_t.flags or amd64_umask_t.flags
  */
-#define AMD64_FAM10H AMD64_FAM10H_REV_B
 typedef enum {
         AMD64_CPU_UN = 0,
         AMD64_K7,
@@ -65,9 +64,16 @@
         AMD64_FAM10H_REV_B,
         AMD64_FAM10H_REV_C,
         AMD64_FAM10H_REV_D,
+        AMD64_FAM11H,
+        AMD64_FAM12H, /* first with Host/Guest filtering */
 
         AMD64_FAM14H_REV_B,
+        AMD64_FAM15H,
+        AMD64_FAM16H,
+        AMD64_FAM17H,
+        AMD64_FAM19H,
 } amd64_rev_t;
+#define AMD64_FAM10H AMD64_FAM10H_REV_B
 
 typedef struct {
         pfm_pmu_t		revision;
@@ -129,6 +135,7 @@
 #define AMD64_FAM14H_ATTRS		AMD64_FAM10H_ATTRS
 #define AMD64_FAM15H_ATTRS		AMD64_FAM10H_ATTRS
 #define AMD64_FAM17H_ATTRS		AMD64_FAM10H_ATTRS
+#define AMD64_FAM19H_ATTRS		AMD64_FAM10H_ATTRS
 
 #define AMD64_FAM10H_PLM	(PFM_PLM0|PFM_PLM3|PFM_PLMH)
 #define AMD64_K7_PLM		(PFM_PLM0|PFM_PLM3)
@@ -179,6 +186,21 @@
 		uint64_t val:1;
 		uint64_t reserved2:45;
 	} ibsop;
+	struct { /* Zen3 L3 */
+		uint64_t event:8;		/* event mask */
+		uint64_t umask:8;		/* unit mask */
+		uint64_t reserved1:6;		/* reserved */
+		uint64_t en:1;			/* enable */
+		uint64_t reserved2:19;		/* reserved */
+		uint64_t core_id:3;		/* Core ID */
+		uint64_t reserved3:1;		/* reserved */
+		uint64_t en_all_slices:1;	/* enable all slices */
+		uint64_t en_all_cores:1;	/* enable all cores */
+		uint64_t slice_id:3;		/* Slice ID */
+		uint64_t reserved4:5;		/* reserved */
+		uint64_t thread_id:4;		/* reserved */
+		uint64_t reserved5:4;		/* reserved */
+	} l3;
 } pfm_amd64_reg_t; /* MSR 0xc001000-0xc001003 */
 
 /* let's define some handy shortcuts! */
@@ -196,9 +218,6 @@
 #define sel_guest	perfsel.sel_guest
 #define sel_host	perfsel.sel_host
 
-#define IS_FAMILY_10H(p) (((pfmlib_pmu_t *)(p))->pmu_rev >= AMD64_FAM10H)
-#define IS_FAMILY_15H(p) (((pfmlib_pmu_t *)(p))->pmu == PFM_PMU_AMD64_FAM15H_INTERLAGOS)
-
 extern int pfm_amd64_get_encoding(void *this, pfmlib_event_desc_t *e);
 extern int pfm_amd64_get_event_first(void *this);
 extern int pfm_amd64_get_event_next(void *this, int idx);
@@ -215,4 +234,10 @@
 extern void pfm_amd64_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e);
 extern void pfm_amd64_nb_perf_validate_pattrs(void *this, pfmlib_event_desc_t *e);
 extern int pfm_amd64_family_detect(void *this);
+
+static inline int pfm_amd64_supports_virt(pfmlib_pmu_t *pmu)
+{
+	return pmu->pmu_rev >= AMD64_FAM10H && pmu->pmu_rev != AMD64_FAM11H;
+}
+
 #endif /* __PFMLIB_AMD64_PRIV_H__ */
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_amd64_rapl.c libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_amd64_rapl.c
--- libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_amd64_rapl.c	1970-01-01 01:00:00.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_amd64_rapl.c	2021-06-09 09:24:16.000000000 +0200
@@ -0,0 +1,121 @@
+/*
+ * pfmlib_amd64_rapl.c : AMD RAPL PMU
+ *
+ * Copyright 2021 Google LLC
+ * Contributed by Stephane Eranian <eranian@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
+ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
+ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * AMD RAPL PMU (AMD Zen2)
+ */
+
+/* private headers */
+#include "pfmlib_priv.h"
+/*
+ * for now, we reuse the x86 table entry format and callback to avoid duplicating
+ * code. We may revisit this later on
+ */
+#include "pfmlib_amd64_priv.h"
+
+extern pfmlib_pmu_t amd64_rapl_support;
+
+static const amd64_entry_t amd64_rapl_zen2[]={
+  { .name   = "RAPL_ENERGY_PKG",
+    .desc   = "Number of Joules consumed by all cores and Last level cache on the package. Unit is 2^-32 Joules",
+    .code   = 0x2,
+  }
+};
+
+static int
+pfm_amd64_rapl_detect(void *this)
+{
+	int ret, rev;
+
+	ret = pfm_amd64_detect(this);
+	if (ret != PFM_SUCCESS)
+		return ret;
+
+	rev = pfm_amd64_cfg.revision;
+	switch(rev) {
+	case PFM_PMU_AMD64_FAM17H_ZEN2:
+		ret = PFM_SUCCESS;
+		break;
+	case PFM_PMU_AMD64_FAM19H_ZEN3:
+		ret = PFM_SUCCESS;
+		break;
+	default:
+		ret = PFM_ERR_NOTSUPP;
+	}
+	return ret;
+}
+
+static int
+pfm_amd64_rapl_get_encoding(void *this, pfmlib_event_desc_t *e)
+
+{
+	const amd64_entry_t *pe;
+
+	pe = this_pe(this);
+
+	e->fstr[0] = '\0';
+
+	e->codes[0] = pe[e->event].code;
+	e->count = 1;
+	evt_strcat(e->fstr, "%s", pe[e->event].name);
+
+	__pfm_vbprintf("[0x%"PRIx64" event=0x%x] %s\n",
+		       e->codes[0],
+		       e->codes[0], e->fstr);
+
+	return PFM_SUCCESS;
+}
+
+/*
+ * number modifiers for RAPL
+ * define an empty modifier to avoid firing the
+ * sanity pfm_amd64_validate_table(). We are
+ * using this function to avoid duplicating code.
+ */
+static const pfmlib_attr_desc_t amd64_rapl_mods[]=
+{ { 0, } };
+
+pfmlib_pmu_t amd64_rapl_support={
+	.desc			= "AMD64 RAPL",
+	.name			= "amd64_rapl",
+	.perf_name		= "power",
+	.pmu			= PFM_PMU_AMD64_RAPL,
+	.pme_count		= LIBPFM_ARRAY_SIZE(amd64_rapl_zen2),
+	.type			= PFM_PMU_TYPE_UNCORE,
+	.num_cntrs		= 0,
+	.num_fixed_cntrs	= 3,
+	.max_encoding		= 1,
+	.pe			= amd64_rapl_zen2,
+	.pmu_detect		= pfm_amd64_rapl_detect,
+	.atdesc			= amd64_rapl_mods,
+
+	.get_event_encoding[PFM_OS_NONE] = pfm_amd64_rapl_get_encoding,
+	 PFMLIB_ENCODE_PERF(pfm_amd64_get_perf_encoding),
+	.get_event_first	= pfm_amd64_get_event_first,
+	.get_event_next		= pfm_amd64_get_event_next,
+	.event_is_valid		= pfm_amd64_event_is_valid,
+	.validate_table		= pfm_amd64_validate_table,
+	.get_event_info		= pfm_amd64_get_event_info,
+	.get_event_attr_info	= pfm_amd64_get_event_attr_info,
+	 PFMLIB_VALID_PERF_PATTRS(pfm_amd64_perf_validate_pattrs),
+	.get_event_nattrs	= pfm_amd64_get_event_nattrs,
+};
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_arm_armv8.c libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_arm_armv8.c
--- libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_arm_armv8.c	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_arm_armv8.c	2021-06-09 09:24:16.000000000 +0200
@@ -254,7 +254,7 @@
 
 	.pmu_detect		= pfm_arm_detect_a64fx,
 	.max_encoding		= 1,
-	.num_cntrs		= 6,
+	.num_cntrs		= 8,
 
 	.get_event_encoding[PFM_OS_NONE] = pfm_arm_get_encoding,
 	 PFMLIB_ENCODE_PERF(pfm_arm_get_perf_encoding),
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_common.c libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_common.c
--- libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_common.c	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_common.c	2021-06-09 09:24:16.000000000 +0200
@@ -81,6 +81,9 @@
 	&amd64_fam17h_deprecated_support,
 	&amd64_fam17h_zen1_support,
 	&amd64_fam17h_zen2_support,
+	&amd64_fam19h_zen3_support,
+	&amd64_fam19h_zen3_l3_support,
+	&amd64_rapl_support,
 	&intel_core_support,
 	&intel_atom_support,
 	&intel_nhm_support,
@@ -109,6 +112,7 @@
 	&intel_skx_support,
 	&intel_clx_support,
 	&intel_icl_support,
+	&intel_icx_support,
 	&intel_rapl_support,
 	&intel_snbep_unc_cb0_support,
 	&intel_snbep_unc_cb1_support,
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_intel_icl.c libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_intel_icl.c
--- libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_intel_icl.c	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_intel_icl.c	2021-06-09 09:24:16.000000000 +0200
@@ -27,11 +27,18 @@
 #include "events/intel_icl_events.h"
 
 static const int icl_models[] = {
-	106, /* IcelakeX */
 	108, /* Icelake D */
 	125, /* Icelake */
 	126, /* Icelake L */
 	157, /* Icelake NNPI */
+	140, /* Tigerlake L */
+	141, /* Tigerlake */
+	167, /* Rocketlake */
+	0
+};
+
+static const int icx_models[] = {
+	106, /* IcelakeX */
 	0
 };
 
@@ -42,6 +49,7 @@
 	return PFM_SUCCESS;
 }
 
+
 pfmlib_pmu_t intel_icl_support={
 	.desc			= "Intel Icelake",
 	.name			= "icl",
@@ -63,6 +71,40 @@
 	.pmu_detect		= pfm_intel_x86_model_detect,
 	.pmu_init		= pfm_icl_init,
 	.get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding,
+	 PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding),
+	.get_event_first	= pfm_intel_x86_get_event_first,
+	.get_event_next		= pfm_intel_x86_get_event_next,
+	.event_is_valid		= pfm_intel_x86_event_is_valid,
+	.validate_table		= pfm_intel_x86_validate_table,
+	.get_event_info		= pfm_intel_x86_get_event_info,
+	.get_event_attr_info	= pfm_intel_x86_get_event_attr_info,
+	 PFMLIB_VALID_PERF_PATTRS(pfm_intel_x86_perf_validate_pattrs),
+	.get_event_nattrs	= pfm_intel_x86_get_event_nattrs,
+	.can_auto_encode	= pfm_intel_x86_can_auto_encode,
+	.get_num_events		= pfm_intel_x86_get_num_events,
+};
+
+pfmlib_pmu_t intel_icx_support={
+	.desc			= "Intel IcelakeX",
+	.name			= "icx",
+	.pmu			= PFM_PMU_INTEL_ICX,
+	.pme_count		= LIBPFM_ARRAY_SIZE(intel_icl_pe),
+	.type			= PFM_PMU_TYPE_CORE,
+	.supported_plm		= INTEL_X86_PLM,
+	.num_cntrs		= 16, /* consider with HT off by default */
+	.num_fixed_cntrs	= 4,
+	.max_encoding		= 2, /* offcore_response */
+	.pe			= intel_icl_pe,
+	.atdesc			= intel_x86_mods,
+	.flags			= PFMLIB_PMU_FL_RAW_UMASK
+				| PFMLIB_PMU_FL_SPEC
+				| INTEL_X86_PMU_FL_ECMASK
+				| INTEL_X86_PMU_FL_EXTPEBS,
+	.cpu_family		= 6,
+	.cpu_models		= icx_models,
+	.pmu_detect		= pfm_intel_x86_model_detect,
+	.pmu_init		= pfm_icl_init,
+	.get_event_encoding[PFM_OS_NONE] = pfm_intel_x86_get_encoding,
 	 PFMLIB_ENCODE_PERF(pfm_intel_x86_get_perf_encoding),
 	.get_event_first	= pfm_intel_x86_get_event_first,
 	.get_event_next		= pfm_intel_x86_get_event_next,
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_intel_nhm_unc.c libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_intel_nhm_unc.c
--- libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_intel_nhm_unc.c	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_intel_nhm_unc.c	2021-06-09 09:24:16.000000000 +0200
@@ -212,7 +212,7 @@
 	 */
 	if ((ugrpmsk != grpmsk && !intel_x86_eflag(this, e->event, INTEL_X86_GRP_EXCL)) || ugrpmsk == 0) {
 		ugrpmsk ^= grpmsk;
-		ret = pfm_intel_x86_add_defaults(this, e, ugrpmsk, &umask, -1, -1);
+		ret = pfm_intel_x86_add_defaults(this, e, ugrpmsk, &umask, (unsigned short) -1, -1);
 		if (ret != PFM_SUCCESS)
 			return ret;
 	}
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_intel_snbep_unc.c libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_intel_snbep_unc.c
--- libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_intel_snbep_unc.c	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_intel_snbep_unc.c	2021-06-09 09:24:16.000000000 +0200
@@ -331,7 +331,7 @@
 						DPRINT("two max_grpid, old=%d new=%d\n", max_grpid, get_grpid(ent->umasks[idx].grpid));
 						return PFM_ERR_UMASK;
 					}
-					max_grpid = ent->umasks[idx].grpid;
+					max_grpid = get_grpid(ent->umasks[idx].grpid);
 				}
 			}
 		}
@@ -483,7 +483,7 @@
 			um >>= 8;
 			umask2  |= um;
 
-			ugrpmsk |= 1 << pe[e->event].umasks[a->idx].grpid;
+			ugrpmsk |= 1 << grpid;
 
 			/* PCU occ event */
 			if (is_occ_event(this, e->event)) {
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_intel_x86_perf_event.c libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_intel_x86_perf_event.c
--- libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_intel_x86_perf_event.c	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_intel_x86_perf_event.c	2021-06-09 09:24:16.000000000 +0200
@@ -82,6 +82,7 @@
 pfm_intel_x86_get_perf_encoding(void *this, pfmlib_event_desc_t *e)
 {
 	pfmlib_pmu_t *pmu = this;
+	pfm_intel_x86_reg_t reg;
 	struct perf_event_attr *attr = e->os_data;
 	int ret;
 
@@ -117,7 +118,20 @@
 		}
 	}
 
-	attr->config = e->codes[0];
+	reg.val = e->codes[0];
+
+	/*
+	 * suppress the bits which are under the control of perf_events
+	 * they will be ignore by the perf tool and the kernel interface
+	 * the OS/USR bits are controlled by the attr.exclude_* fields
+	 * the EN/INT bits are controlled by the kernel
+	 */
+	reg.sel_en   = 0;
+	reg.sel_int  = 0;
+	reg.sel_os   = 0;
+	reg.sel_usr  = 0;
+
+	attr->config = reg.val;
 
 	if (e->count > 1) {
 		/*
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_perf_event.c libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_perf_event.c
--- libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_perf_event.c	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_perf_event.c	2021-06-09 09:24:16.000000000 +0200
@@ -256,7 +256,7 @@
 	attr->pinned	     = pinned;
 
 	__pfm_vbprintf("PERF[type=%x config=0x%"PRIx64" config1=0x%"PRIx64
-                       " excl=%d e_u=%d e_k=%d e_hv=%d e_host=%d e_gu=%d period=%"PRIu64" freq=%d"
+                       " excl=%d excl_user=%d excl_kernel=%d excl_hv=%d excl_host=%d excl_guest=%d period=%"PRIu64" freq=%d"
                        " precise=%d pinned=%d] %s\n",
 			attr->type,
 			attr->config,
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_perf_event_pmu.c libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_perf_event_pmu.c
--- libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_perf_event_pmu.c	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_perf_event_pmu.c	2021-06-09 09:24:16.000000000 +0200
@@ -74,7 +74,7 @@
 #define PERF_FL_DEFAULT	0x1	/* umask is default for group */
 #define PERF_FL_PRECISE	0x2	/* support precise sampling */
 
-#define PERF_INVAL_OVFL_IDX ((unsigned long)-1)
+#define PERF_INVAL_OVFL_IDX (~0UL)
 
 #define PCL_EVT(f, t, m, fl)	\
 	{ .name = #f,		\
@@ -385,7 +385,7 @@
 		}
 
 		p->desc = "tracepoint";
-		p->id = -1;
+		p->id = ~0ULL;
 		p->type = PERF_TYPE_TRACEPOINT;
 		p->umask_ovfl_idx = PERF_INVAL_OVFL_IDX;
 		p->modmsk = 0,
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_priv.h libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_priv.h
--- libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_priv.h	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_priv.h	2021-06-09 09:24:16.000000000 +0200
@@ -255,6 +255,9 @@
 extern pfmlib_pmu_t amd64_fam17h_deprecated_support;
 extern pfmlib_pmu_t amd64_fam17h_zen1_support;
 extern pfmlib_pmu_t amd64_fam17h_zen2_support;
+extern pfmlib_pmu_t amd64_fam19h_zen3_support;
+extern pfmlib_pmu_t amd64_fam19h_zen3_l3_support;
+extern pfmlib_pmu_t amd64_rapl_support;
 extern pfmlib_pmu_t intel_p6_support;
 extern pfmlib_pmu_t intel_ppro_support;
 extern pfmlib_pmu_t intel_pii_support;
@@ -289,6 +292,7 @@
 extern pfmlib_pmu_t intel_skx_support;
 extern pfmlib_pmu_t intel_clx_support;
 extern pfmlib_pmu_t intel_icl_support;
+extern pfmlib_pmu_t intel_icx_support;
 extern pfmlib_pmu_t intel_rapl_support;
 extern pfmlib_pmu_t intel_snbep_unc_cb0_support;
 extern pfmlib_pmu_t intel_snbep_unc_cb1_support;
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_s390x_perf_event.c libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_s390x_perf_event.c
--- libpfm4-4.11.1+git8-gc96ebc0/lib/pfmlib_s390x_perf_event.c	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/lib/pfmlib_s390x_perf_event.c	2021-06-09 09:24:16.000000000 +0200
@@ -44,27 +44,61 @@
  *
  * As the CPU Measurement counter facility does not change on a running
  * system, read out the type value on first read and cache it.
+ *
+ * There are several PMUs for s390, so find the correct one first and return
+ * its PMU type value assigned at system boot time.
  */
-#define CPUM_CF_DEVICE_TYPE  "/sys/bus/event_source/devices/cpum_cf/type"
-static int cpum_cf_type;
-static int pfm_s390_get_perf_attr_type(void)
+static struct pfm_s390_perf_aptt {	/* Perf attribute PMU type table */
+	pfm_pmu_t pmutype;		/* PMU Type number */
+	const char *fname;		/* File name to read type from */
+	unsigned int value;		/* Type value, 0 --> unused */
+} pfm_s390_perf_aptt[] = {
+	{
+		.pmutype = PFM_PMU_S390X_CPUM_CF,
+		.fname = "/sys/bus/event_source/devices/cpum_cf/type"
+	},
+	{
+		.pmutype = PFM_PMU_S390X_CPUM_SF,
+		.fname = "/sys/bus/event_source/devices/cpum_sf/type"
+	},
+};
+#define S390_APTT_COUNT LIBPFM_ARRAY_SIZE(pfm_s390_perf_aptt)
+
+static int pfm_s390_get_perf_attr_type(pfm_pmu_t pmutype)
 {
+	int cpum_cf_type;
 	size_t buflen;
 	char *buffer;
 	FILE *fp;
+	size_t i;
+
+	/* Find type of PMU and return known and cached value */
+	for (i = 0; i < S390_APTT_COUNT; ++i) {
+		if (pfm_s390_perf_aptt[i].pmutype == pmutype)
+			break;
+	}
+
+	if (i == S390_APTT_COUNT)
+		return PFM_ERR_NOTFOUND;
 
-	if (cpum_cf_type)
-		return cpum_cf_type;
+	if (pfm_s390_perf_aptt[i].value)
+		return pfm_s390_perf_aptt[i].value;
 
-	fp = fopen(CPUM_CF_DEVICE_TYPE, "r");
+	/* Value unknown, read from file */
+	fp = fopen(pfm_s390_perf_aptt[i].fname, "r");
 	if (fp == NULL)
-		return cpum_cf_type;
+		return PFM_ERR_NOTFOUND;
+
 	buffer = NULL;
+
 	if (pfmlib_getl(&buffer, &buflen, fp) != -1 &&
 	    sscanf(buffer, "%u", &cpum_cf_type) == -1)
 		cpum_cf_type = PERF_TYPE_RAW;
+
 	fclose(fp);
 	free(buffer);
+
+	pfm_s390_perf_aptt[i].value = cpum_cf_type;
 	return cpum_cf_type;
 }
 
@@ -81,8 +115,12 @@
 	rc = pmu->get_event_encoding[PFM_OS_NONE](this, e);
 	if (rc == PFM_SUCCESS) {
 		/* currently use raw events only */
-		attr->type = pfm_s390_get_perf_attr_type();
-		attr->config = e->codes[0];
+		rc = pfm_s390_get_perf_attr_type(pmu->pmu);
+		if (rc > 0) {		/* PMU types are positive */
+			attr->type = rc;
+			attr->config = e->codes[0];
+			rc = PFM_SUCCESS;
+		}
 	}
 
 	return rc;
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/perf_examples/notify_group.c libpfm4-4.11.1+git32-gd0b85fb/perf_examples/notify_group.c
--- libpfm4-4.11.1+git8-gc96ebc0/perf_examples/notify_group.c	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/perf_examples/notify_group.c	2021-06-09 09:24:16.000000000 +0200
@@ -122,7 +122,7 @@
 	 * Install the signal handler (SIGIO)
 	 */
 	memset(&act, 0, sizeof(act));
-	act.sa_sigaction = (void *)sigio_handler;
+	act.sa_sigaction = (void (*)(int, siginfo_t *, void *)) sigio_handler;
 	act.sa_flags = SA_SIGINFO;
 	sigaction (SIGIO, &act, 0);
 
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/perf_examples/perf_util.c libpfm4-4.11.1+git32-gd0b85fb/perf_examples/perf_util.c
--- libpfm4-4.11.1+git8-gc96ebc0/perf_examples/perf_util.c	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/perf_examples/perf_util.c	2021-06-09 09:24:16.000000000 +0200
@@ -270,7 +270,7 @@
 	ret = perf_read_buffer_32(hw, &raw_sz);
 	if (ret) {
 		warnx("cannot read raw size");
-		return -1;
+		return (size_t)-1;
 	}
 
 	sz += sizeof(raw_sz);
@@ -280,7 +280,7 @@
 	buf = malloc(raw_sz);
 	if (!buf) {
 		warn("cannot allocate raw buffer");
-		return -1;
+		return (size_t)-1;
 	}
 
 
@@ -288,7 +288,7 @@
 	if (ret) {
 		warnx("cannot read raw data");
 		free(buf);
-		return -1;
+		return (size_t)-1;
 	}
 
 	if (raw_sz)
@@ -571,7 +571,7 @@
 			values[1] = time_enabled;
 			values[2] = time_running;
 			while(nr--) {
-				grp.id = -1;
+				grp.id = ~0ULL;
 				ret = perf_read_buffer_64(hw, &grp.value);
 				if (ret) {
 					warnx( "cannot read group value");
diff -Nru libpfm4-4.11.1+git8-gc96ebc0/tests/validate_x86.c libpfm4-4.11.1+git32-gd0b85fb/tests/validate_x86.c
--- libpfm4-4.11.1+git8-gc96ebc0/tests/validate_x86.c	2020-12-10 04:49:59.000000000 +0100
+++ libpfm4-4.11.1+git32-gd0b85fb/tests/validate_x86.c	2021-06-09 09:24:16.000000000 +0200
@@ -6012,6 +6012,15 @@
 	  .fstr = "skx_unc_cha0::UNC_C_TOR_INSERTS:IRQ:OPC0_DRD:OPC1_RFO:e=0:i=0:t=0:isoc=0:nc=0:loc=0:rem=0:lmem=0:rmem=0",
 	},
 	{ SRC_LINE,
+	  .name = "skx_unc_cha0::UNC_C_TOR_INSERTS:IPQ:OPC0_SNP_CUR",
+	  .ret  = PFM_SUCCESS,
+	  .count = 3,
+	  .codes[0] = 0x0835,
+	  .codes[1] = 0x0,
+	  .codes[2] = 0x30000,
+	  .fstr = "skx_unc_cha0::UNC_C_TOR_INSERTS:IPQ:OPC0_SNP_CUR:e=0:i=0:t=0:isoc=0:nc=0:loc=0:rem=0:lmem=0:rmem=0",
+	},
+	{ SRC_LINE,
 	  .name = "skx_unc_cha0::UNC_C_LLC_LOOKUP:LOCAL:DATA_READ",
 	  .ret  = PFM_SUCCESS,
 	  .count = 2,
@@ -7279,6 +7288,341 @@
 	  .name = "icl::mem_trans_retired:load_latency:ldlat=2:intx=0:intxcp=0",
 	  .ret = PFM_ERR_ATTR_VAL,
 	},
+	{ SRC_LINE,
+	  .name = "amd64_fam19h_zen3::retired_ops",
+	  .count = 1,
+	  .codes[0] = 0x5300c1ull,
+	  .fstr = "amd64_fam19h_zen3::RETIRED_OPS:k=1:u=1:e=0:i=0:c=0:h=0:g=0",
+	},
+	{ SRC_LINE,
+	  .name = "amd64_fam19h_zen3::cycles_not_in_halt",
+	  .count = 1,
+	  .codes[0] = 0x530076ull,
+	  .fstr = "amd64_fam19h_zen3::CYCLES_NOT_IN_HALT:k=1:u=1:e=0:i=0:c=0:h=0:g=0",
+	},
+	{ SRC_LINE,
+	  .name = "amd64_fam19h_zen3::L2_PREFETCH_HIT_L2",
+	  .count = 1,
+	  .codes[0] = 0x530070ull,
+	  .fstr = "amd64_fam19h_zen3::L2_PREFETCH_HIT_L2:k=1:u=1:e=0:i=0:c=0:h=0:g=0",
+	},
+	{ SRC_LINE,
+	  .name = "amd64_fam19h_zen3::L1_DTLB_MISS:TLB_RELOAD_1G_L2_HIT:u",
+	  .count = 1,
+	  .codes[0] = 0x510845ull,
+	  .fstr = "amd64_fam19h_zen3::L1_DTLB_MISS:TLB_RELOAD_1G_L2_HIT:k=0:u=1:e=0:i=0:c=0:h=0:g=0",
+	},
+	{ SRC_LINE,
+	  .name = "amd64_fam19h_zen3::RETIRED_FUSED_INSTRUCTIONS",
+	  .count = 1,
+	  .codes[0] = 0x1005300d0ull,
+	  .fstr = "amd64_fam19h_zen3::RETIRED_FUSED_INSTRUCTIONS:k=1:u=1:e=0:i=0:c=0:h=0:g=0",
+	},
+	{ SRC_LINE,
+	  .name = "amd64_fam19h_zen3::RETIRED_SSE_AVX_FLOPS",
+	  .count = 1,
+	  .codes[0] = 0x530f03ull,
+	  .fstr = "amd64_fam19h_zen3::RETIRED_SSE_AVX_FLOPS:ANY:k=1:u=1:e=0:i=0:c=0:h=0:g=0",
+	},
+	{ SRC_LINE,
+	  .name = "amd64_fam19h_zen3::RETIRED_SSE_AVX_FLOPS:MULT_FLOPS:u",
+	  .count = 1,
+	  .codes[0] = 0x510203ull,
+	  .fstr = "amd64_fam19h_zen3::RETIRED_SSE_AVX_FLOPS:MULT_FLOPS:k=0:u=1:e=0:i=0:c=0:h=0:g=0",
+	},
+	{ SRC_LINE,
+	  .name = "amd64_fam19h_zen3_l3::UNC_L3_REQUESTS",
+	  .count = 1,
+	  .codes[0] = 0x53ff04ull,
+	  .fstr = "amd64_fam19h_zen3_l3::UNC_L3_REQUESTS:ALL",
+	},
+	{ SRC_LINE,
+	  .name = "amd64_fam19h_zen3_l3::UNC_L3_REQUESTS:u",
+	  .ret  = PFM_ERR_ATTR,
+	},
+	{ SRC_LINE,
+	  .name = "amd64_fam19h_zen3_l3::UNC_L3_MISSES",
+	  .count = 1,
+	  .codes[0] = 0x53ff9aull,
+	  .fstr = "amd64_fam19h_zen3_l3::UNC_L3_MISSES:ALL",
+	},
+	{ SRC_LINE,
+	  .name = "icx::FRONTEND_RETIRED:DSB_MISS",
+	  .ret  = PFM_SUCCESS,
+	  .count = 2,
+	  .codes[0] = 0x5301c6,
+	  .codes[1] = 0x11,
+	  .fstr = "icx::FRONTEND_RETIRED:DSB_MISS:k=1:u=1:e=0:i=0:c=0:intx=0:intxcp=0:fe_thres=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::MEM_LOAD_RETIRED:L3_MISS",
+	  .ret  = PFM_SUCCESS,
+	  .count = 1,
+	  .codes[0] = 0x5320d1,
+	  .fstr = "icx::MEM_LOAD_RETIRED:L3_MISS:k=1:u=1:e=0:i=0:c=0:intx=0:intxcp=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::CPU_CLK_UNHALTED.DISTRIBUTED",
+	  .ret  = PFM_SUCCESS,
+	  .count = 1,
+	  .codes[0] = 0x5302ec,
+	  .fstr = "icx::CPU_CLK_UNHALTED:DISTRIBUTED:k=1:u=1:e=0:i=0:c=0:intx=0:intxcp=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::CPU_CLK_UNHALTED.REF_DISTRIBUTED",
+	  .ret  = PFM_SUCCESS,
+	  .count = 1,
+	  .codes[0] = 0x5308ec,
+	  .fstr = "icx::CPU_CLK_UNHALTED:REF_DISTRIBUTED:k=1:u=1:e=0:i=0:c=0:intx=0:intxcp=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::FRONTEND_RETIRED:ITLB_MISS",
+	  .ret  = PFM_SUCCESS,
+	  .count = 2,
+	  .codes[0] = 0x5301c6,
+	  .codes[1] = 0x14,
+	  .fstr = "icx::FRONTEND_RETIRED:ITLB_MISS:k=1:u=1:e=0:i=0:c=0:intx=0:intxcp=0:fe_thres=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::FRONTEND_RETIRED:L1I_MISS",
+	  .ret  = PFM_SUCCESS,
+	  .count = 2,
+	  .codes[0] = 0x5301c6,
+	  .codes[1] = 0x12,
+	  .fstr = "icx::FRONTEND_RETIRED:L1I_MISS:k=1:u=1:e=0:i=0:c=0:intx=0:intxcp=0:fe_thres=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::FRONTEND_RETIRED:L2_MISS:u",
+	  .ret  = PFM_SUCCESS,
+	  .count = 2,
+	  .codes[0] = 0x5101c6,
+	  .codes[1] = 0x13,
+	  .fstr = "icx::FRONTEND_RETIRED:L2_MISS:k=0:u=1:e=0:i=0:c=0:intx=0:intxcp=0:fe_thres=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::FRONTEND_RETIRED:STLB_MISS:c=1:i",
+	  .ret  = PFM_SUCCESS,
+	  .count = 2,
+	  .codes[0] = 0x1d301c6,
+	  .codes[1] = 0x15,
+	  .fstr = "icx::FRONTEND_RETIRED:STLB_MISS:k=1:u=1:e=0:i=1:c=1:intx=0:intxcp=0:fe_thres=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::FRONTEND_RETIRED:LATENCY_GE_256",
+	  .ret  = PFM_SUCCESS,
+	  .count = 2,
+	  .codes[0] = 0x5301c6,
+	  .codes[1] = 0x510006,
+	  .fstr = "icx::FRONTEND_RETIRED:LATENCY_GE_256:k=1:u=1:e=0:i=0:c=0:intx=0:intxcp=0:fe_thres=256",
+	},
+	{ SRC_LINE,
+	  .name = "icx::FRONTEND_RETIRED:LATENCY_GE_2_BUBBLES_GE_1",
+	  .ret  = PFM_SUCCESS,
+	  .count = 2,
+	  .codes[0] = 0x5301c6,
+	  .codes[1] = 0x100206,
+	  .fstr = "icx::FRONTEND_RETIRED:LATENCY_GE_2_BUBBLES_GE_1:k=1:u=1:e=0:i=0:c=0:intx=0:intxcp=0:fe_thres=2",
+	},
+	{ SRC_LINE,
+	  .name = "icx::FRONTEND_RETIRED:LATENCY_GE_4:fe_thres=4095",
+	  .ret  = PFM_ERR_ATTR_SET,
+	},
+	{ SRC_LINE,
+	  .name = "icx::FRONTEND_RETIRED:IDQ_2_BUBBLES:k",
+	  .ret  = PFM_SUCCESS,
+	  .count = 2,
+	  .codes[0] = 0x5201c6,
+	  .codes[1] = 0x200106,
+	  .fstr = "icx::FRONTEND_RETIRED:IDQ_2_BUBBLES:k=1:u=0:e=0:i=0:c=0:intx=0:intxcp=0:fe_thres=1",
+	},
+	{ SRC_LINE,
+	  .name = "icx::FRONTEND_RETIRED:IDQ_4_BUBBLES:fe_thres=4095",
+	  .ret  = PFM_SUCCESS,
+	  .count = 2,
+	  .codes[0] = 0x5301c6,
+	  .codes[1] = 0x4fff06,
+	  .fstr = "icx::FRONTEND_RETIRED:IDQ_4_BUBBLES:k=1:u=1:e=0:i=0:c=0:intx=0:intxcp=0:fe_thres=4095",
+	},
+	{ SRC_LINE,
+	  .name = "icx::FRONTEND_RETIRED:IDQ_4_BUBBLES:fe_thres=4096",
+	  .ret  = PFM_ERR_ATTR_VAL,
+	},
+	{ SRC_LINE,
+	  .name = "icx::FRONTEND_RETIRED:DSB_MISS:ITLB_MISS",
+	  .ret  = PFM_ERR_FEATCOMB,
+	},
+	{ SRC_LINE,
+	  .name = "icx::offcore_response_0:demand_Data_rd_local_dram",
+	  .ret  = PFM_SUCCESS,
+	  .count = 2,
+	  .codes[0] = 0x5301b7,
+	  .codes[1] = 0x184000001ull,
+	  .fstr = "icx::OFFCORE_RESPONSE_0:DEMAND_DATA_RD_LOCAL_DRAM:k=1:u=1:e=0:i=0:c=0:intx=0:intxcp=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::offcore_response_0:demand_rfo_l3_miss",
+	  .ret  = PFM_SUCCESS,
+	  .count = 2,
+	  .codes[0] = 0x5301b7,
+	  .codes[1] = 0x3fffc00002ull,
+	  .fstr = "icx::OFFCORE_RESPONSE_0:DEMAND_RFO_L3_MISS:k=1:u=1:e=0:i=0:c=0:intx=0:intxcp=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::offcore_response_0:other_any_response",
+	  .ret  = PFM_SUCCESS,
+	  .count = 2,
+	  .codes[0] = 0x5301b7,
+	  .codes[1] = 0x18000ull,
+	  .fstr = "icx::OFFCORE_RESPONSE_0:OTHER_ANY_RESPONSE:k=1:u=1:e=0:i=0:c=0:intx=0:intxcp=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::offcore_response_0:DEMAND_DATA_RD_L3_HIT_SNOOP_HITM",
+	  .ret  = PFM_SUCCESS,
+	  .count = 2,
+	  .codes[0] = 0x5301b7,
+	  .codes[1] = 0x10003c0001ull,
+	  .fstr = "icx::OFFCORE_RESPONSE_0:DEMAND_DATA_RD_L3_HIT_SNOOP_HITM:k=1:u=1:e=0:i=0:c=0:intx=0:intxcp=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::offcore_response_0:STREAMING_WR_LOCAL_DRAM",
+	  .ret = PFM_SUCCESS,
+	  .count = 2,
+	  .codes[0] = 0x5301b7,
+	  .codes[1] = 0x184000800ull,
+	  .fstr = "icx::OFFCORE_RESPONSE_0:STREAMING_WR_LOCAL_DRAM:k=1:u=1:e=0:i=0:c=0:intx=0:intxcp=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::cycle_activity:0x6:c=6",
+	  .count = 1,
+	  .codes[0] = 0x65306a3,
+	  .fstr = "icx::CYCLE_ACTIVITY:0x6:k=1:u=1:e=0:i=0:c=6:intx=0:intxcp=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::dtlb_store_misses:walk_completed_2m_4m:c=1",
+	  .count = 1,
+	  .codes[0] = 0x1530449,
+	  .fstr = "icx::DTLB_STORE_MISSES:WALK_COMPLETED_2M_4M:k=1:u=1:e=0:i=0:c=1:intx=0:intxcp=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::rob_misc_events:lbr_inserts",
+	  .ret = PFM_ERR_NOTFOUND,
+	  .count = 1,
+	  .codes[0] = 0x5320cc,
+	  .fstr = "icx::ROB_MISC_EVENTS:LBR_INSERTS:k=1:u=1:e=0:i=0:c=0:intx=0:intxcp=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::misc_retired:lbr_inserts",
+	  .count = 1,
+	  .codes[0] = 0x5320cc,
+	  .fstr = "icx::MISC_RETIRED:LBR_INSERTS:k=1:u=1:e=0:i=0:c=0:intx=0:intxcp=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::cycle_activity:stalls_mem_any:c=6",
+	  .ret = PFM_ERR_ATTR_SET,
+	},
+	{ SRC_LINE,
+	  .name = "icx::uops_dispatched_port:port_0",
+	  .count = 1,
+	  .codes[0] = 0x5301a1,
+	  .fstr = "icx::UOPS_DISPATCHED:PORT_0:k=1:u=1:e=0:i=0:c=0:intx=0:intxcp=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::uops_dispatched:port_0",
+	  .count = 1,
+	  .codes[0] = 0x5301a1,
+	  .fstr = "icx::UOPS_DISPATCHED:PORT_0:k=1:u=1:e=0:i=0:c=0:intx=0:intxcp=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::l2_lines_out.useless_hwpf",
+	  .count = 1,
+	  .codes[0] = 0x5304f2,
+	  .fstr = "icx::L2_LINES_OUT:USELESS_HWPF:k=1:u=1:e=0:i=0:c=0:intx=0:intxcp=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::l2_lines_out.silent:t=0",
+	  .ret  = PFM_ERR_ATTR,
+	},
+	{ SRC_LINE,
+	  .name = "icx::inst_retired:stall_cycles",
+	  .ret  = PFM_SUCCESS,
+	  .count = 1,
+	  .codes[0] = 0x1d301c0,
+	  .fstr = "icx::INST_RETIRED:STALL_CYCLES:k=1:u=1:e=0:i=1:c=1:intx=0:intxcp=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::inst_retired:stall_cycles",
+	  .ret  = PFM_SUCCESS,
+	  .count = 1,
+	  .codes[0] = 0x1d301c0,
+	  .fstr = "icx::INST_RETIRED:STALL_CYCLES:k=1:u=1:e=0:i=1:c=1:intx=0:intxcp=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::inst_retired:prec_dist",
+	  .ret  = PFM_SUCCESS,
+	  .count = 1,
+	  .codes[0] = 0x530100,
+	  .fstr = "icx::INST_RETIRED:PREC_DIST:k=1:u=1:e=0:i=0:c=0:intx=0:intxcp=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::inst_retired:any_p",
+	  .ret  = PFM_SUCCESS,
+	  .count = 1,
+	  .codes[0] = 0x5300c0,
+	  .fstr = "icx::INST_RETIRED:ANY_P:k=1:u=1:e=0:i=0:c=0:intx=0:intxcp=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::inst_retired:any",
+	  .ret  = PFM_SUCCESS,
+	  .count = 1,
+	  .codes[0] = 0x530100,
+	  .fstr = "icx::INST_RETIRED:ANY:k=1:u=1:e=0:i=0:c=0:intx=0:intxcp=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::mem_trans_retired:load_latency:ldlat=3:u",
+	  .ret = PFM_SUCCESS,
+	  .count = 2,
+	  .codes[0] = 0x5101cd,
+	  .codes[1] = 3,
+	  .fstr = "icx::MEM_TRANS_RETIRED:LOAD_LATENCY:k=0:u=1:e=0:i=0:c=0:ldlat=3:intx=0:intxcp=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::mem_trans_retired:load_latency:ldlat=1000000",
+	  .ret = PFM_ERR_ATTR_VAL,
+	},
+	{ SRC_LINE,
+	  .name = "icx::mem_trans_retired:load_latency",
+	  .ret = PFM_SUCCESS,
+	  .count = 2,
+	  .codes[0] = 0x5301cd,
+	  .codes[1] = 3,
+	  .fstr = "icx::MEM_TRANS_RETIRED:LOAD_LATENCY:k=1:u=1:e=0:i=0:c=0:ldlat=3:intx=0:intxcp=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::mem_load_l3_miss_retired:remote_pmm",
+	  .ret = PFM_SUCCESS,
+	  .count = 1,
+	  .codes[0] = 0x5310d3,
+	  .fstr = "icx::MEM_LOAD_L3_MISS_RETIRED:REMOTE_PMM:k=1:u=1:e=0:i=0:c=0:intx=0:intxcp=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::mem_load_l3_miss_retired:remote_pmm",
+	  .ret = PFM_SUCCESS,
+	  .count = 1,
+	  .codes[0] = 0x5310d3,
+	  .fstr = "icx::MEM_LOAD_L3_MISS_RETIRED:REMOTE_PMM:k=1:u=1:e=0:i=0:c=0:intx=0:intxcp=0",
+	},
+	{ SRC_LINE,
+	  .name = "icx::mem_load_l3_miss_retired:remote_dram",
+	  .ret = PFM_SUCCESS,
+	  .count = 1,
+	  .codes[0] = 0x5302d3,
+	  .fstr = "icx::MEM_LOAD_L3_MISS_RETIRED:REMOTE_DRAM:k=1:u=1:e=0:i=0:c=0:intx=0:intxcp=0",
+	},
+	{ SRC_LINE,
+	  .name = "icl::mem_load_l3_miss_retired:remote_dram",
+	  .ret = PFM_ERR_ATTR,
+	  .count = 1,
+	},
 };
 
 #define NUM_TEST_EVENTS (int)(sizeof(x86_test_events)/sizeof(test_event_t))
