From 90b82a3069bf4f7711eb7279bcff73e3d1bf2a84 Mon Sep 17 00:00:00 2001 From: =?utf-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 11 Sep 2009 20:21:10 +0200 Subject: [PATCH] drm/radeon/kms: add power management states storage MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Signed-off-by: Rafał Miłecki --- drivers/gpu/drm/radeon/radeon.h | 13 +++++++++++++ drivers/gpu/drm/radeon/radeon_atombios.c | 15 +++++++++++++++ 2 files changed, 28 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 14c312a..40beff0 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -525,6 +525,12 @@ struct radeon_wb { uint64_t gpu_addr; }; +struct radeon_pm_state { + uint32_t engine_clock; + uint32_t memory_clock; + uint32_t voltage; +}; + /** * struct radeon_pm - power management datas * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) @@ -538,6 +544,9 @@ struct radeon_wb { * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) * @sclk: GPU clock Mhz (core bandwith depends of this clock) * @needed_bandwidth: current bandwidth needs + * @chip_default: original gpu state + * @chip_minimum: minimum gpu state + * @chip_maximum: maximum gpu state * * It keeps track of various data needed to take powermanagement decision. * Bandwith need is used to determine minimun clock of the GPU and memory. @@ -556,6 +565,10 @@ struct radeon_pm { fixed20_12 core_bandwidth; fixed20_12 sclk; fixed20_12 needed_bandwidth; + + struct radeon_pm_state chip_default; + struct radeon_pm_state chip_minimum; + struct radeon_pm_state chip_maximum; }; diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index 233d79e..82342e5 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c @@ -714,6 +714,21 @@ bool radeon_atom_get_clock_info(struct drm_device *dev) rdev->clock.default_mclk = le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); + rdev->pm.chip_default.engine_clock = + firmware_info->info.ulDefaultEngineClock; + rdev->pm.chip_default.memory_clock = + firmware_info->info.ulDefaultMemoryClock; + + rdev->pm.chip_maximum.engine_clock = + firmware_info->info.ulASICMaxEngineClock; + rdev->pm.chip_maximum.memory_clock = + firmware_info->info.ulASICMaxMemoryClock; + + rdev->pm.chip_minimum.engine_clock = + firmware_info->info.usMinEngineClockPLL_Output / 2; + rdev->pm.chip_minimum.memory_clock = + firmware_info->info.usMinMemoryClockPLL_Output / 2; + return true; } return false; -- 1.6.0.2