On Tue, Feb 15, 2011 at 23:46, Andrew Lunn <and...@lunn.ch> wrote: > On Tue, Feb 15, 2011 at 12:47:49PM -0600, Andrew Dyer wrote: >> You have to be very careful doing this. At least some NAND flash >> parts have restrictions on how many 'partial page program' cycles you >> can do. For the part I am using, the restriction is 4 for normal >> memory pages, and 8 for the one time programmable area. > > Hi Andrew > > So for the none one-time blocks, after 4 partial writes you need to do > an erase, before you can do more partial rights? Or are you saying > only 4 ever? > > What part is this?
This is a recent Micron 2Gb large page NAND (I don't have the datasheet handy, but I believe it was the M60A generation). The limitation is that you can do 4 partial writes and then you must do an erase. If you search for 'partial page NAND' you'll get a series of hits from different vendors. The link below is for a conference presentation from Micron. In the section about bit disturb they explain what's happening to prevent unlimited writing. http://www.broadbandreports.com/r0/download/1507743~59e7b9dda2c0e0a0f7ff119a7611c641/flash_mem_summit_jcooke_inconvenient_truths_nand.pdf As another data point, the link below discusses limitations in doing this with a Spansion NOR multiple bit/cell NOR flash: http://www.spansion.com/Support/AppNotes/BitFieldProgMirrorBit_AN_A1_e.pdf -- Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss