From a8a8243dce36ca01e993b422f201ec0348c2d995 Mon Sep 17 00:00:00 2001 From: Eugene Cohen Date: Thu, 21 Mar 2013 09:21:31 -0600 Subject: [PATCH 2/2] enable proper linker dead code stripping for ArmLib by placing each assembly function in its own section --- .../Library/ArmLib/ArmV7/ArmLibSupportV7.asm | 29 +++++--- edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm | 84 +++++++++++++++------- .../ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm | 70 +++++++++++------- 3 files changed, 122 insertions(+), 61 deletions(-) diff --git a/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm b/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm index 39d6c85..a3d1360 100644 --- a/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm +++ b/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm @@ -26,11 +26,10 @@ EXPORT ReadCCSIDR EXPORT ReadCLIDR - AREA ArmLibSupportV7, CODE, READONLY - //------------------------------------------------------------------------------ + AREA s_ArmIsMpCore, CODE, READONLY ArmIsMpCore mrc p15,0,R0,c0,c0,5 // Get Multiprocessing extension (bit31) & U bit (bit30) @@ -39,46 +38,55 @@ ArmIsMpCore and R0, R0, #0x80000000 bx LR + AREA s_ArmEnableAsynchronousAbort, CODE, READONLY ArmEnableAsynchronousAbort cpsie a isb bx LR - + + AREA s_ArmDisableAsynchronousAbort, CODE, READONLY ArmDisableAsynchronousAbort cpsid a isb bx LR - + + AREA s_ArmEnableIrq, CODE, READONLY ArmEnableIrq cpsie i isb bx LR - + + AREA s_ArmDisableIrq, CODE, READONLY ArmDisableIrq cpsid i isb bx LR - + + AREA s_ArmEnableFiq, CODE, READONLY ArmEnableFiq cpsie f isb bx LR - + + AREA s_ArmDisableFiq, CODE, READONLY ArmDisableFiq cpsid f isb bx LR - + + AREA s_ArmEnableInterrupts, CODE, READONLY ArmEnableInterrupts cpsie if isb bx LR - + + AREA s_ArmDisableInterrupts, CODE, READONLY ArmDisableInterrupts cpsid if isb bx LR + AREA s_ReadCCSIDR, CODE, READONLY // UINT32 // ReadCCSIDR ( // IN UINT32 CSSELR @@ -89,6 +97,7 @@ ReadCCSIDR mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR) bx lr + AREA s_ReadCLIDR, CODE, READONLY // UINT32 // ReadCLIDR ( // IN UINT32 CSSELR @@ -97,4 +106,4 @@ ReadCLIDR mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register bx lr -END + END diff --git a/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm b/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm index 8035400..a644105 100644 --- a/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm +++ b/edk2/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm @@ -51,8 +51,8 @@ EXPORT ArmIsArchTimerImplemented EXPORT ArmReadIdPfr1 - AREA ArmV7Support, CODE, READONLY PRESERVE8 + DC_ON EQU ( 0x1:SHL:2 ) IC_ON EQU ( 0x1:SHL:12 ) @@ -61,53 +61,55 @@ CTRL_C_BIT EQU (1 << 2) CTRL_B_BIT EQU (1 << 7) CTRL_I_BIT EQU (1 << 12) - + AREA s_ArmInvalidateDataCacheEntryByMVA, CODE, READONLY ArmInvalidateDataCacheEntryByMVA mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line dsb isb bx lr + AREA s_ArmCleanDataCacheEntryByMVA, CODE, READONLY ArmCleanDataCacheEntryByMVA mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line dsb isb bx lr - + AREA s_ArmCleanInvalidateDataCacheEntryByMVA, CODE, READONLY ArmCleanInvalidateDataCacheEntryByMVA mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line dsb isb bx lr - + AREA s_ArmInvalidateDataCacheEntryBySetWay, CODE, READONLY ArmInvalidateDataCacheEntryBySetWay mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line dsb isb bx lr - + AREA s_ArmCleanInvalidateDataCacheEntryBySetWay, CODE, READONLY ArmCleanInvalidateDataCacheEntryBySetWay mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line dsb isb bx lr - + AREA s_ArmCleanInvalidateDataCacheEntryBySetWay, CODE, READONLY ArmCleanDataCacheEntryBySetWay mcr p15, 0, r0, c7, c10, 2 ; Clean this line dsb isb bx lr - + AREA s_ArmInvalidateInstructionCache, CODE, READONLY ArmInvalidateInstructionCache mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache isb bx LR + AREA s_ArmEnableMmu, CODE, READONLY ArmEnableMmu mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU @@ -116,6 +118,7 @@ ArmEnableMmu isb bx LR + AREA s_ArmDisableMmu, CODE, READONLY ArmDisableMmu mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU @@ -127,6 +130,7 @@ ArmDisableMmu isb bx LR + AREA s_ArmDisableCachesAndMmu, CODE, READONLY ArmDisableCachesAndMmu mrc p15, 0, r0, c1, c0, 0 ; Get control register bic r0, r0, #CTRL_M_BIT ; Disable MMU @@ -137,11 +141,13 @@ ArmDisableCachesAndMmu isb bx LR + AREA s_ArmMmuEnabled, CODE, READONLY ArmMmuEnabled mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) and R0,R0,#1 bx LR + AREA s_ArmEnableDataCache, CODE, READONLY ArmEnableDataCache ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) @@ -151,6 +157,7 @@ ArmEnableDataCache isb bx LR + AREA s_ArmDisableDataCache, CODE, READONLY ArmDisableDataCache ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) @@ -159,7 +166,8 @@ ArmDisableDataCache dsb isb bx LR - + + AREA s_ArmEnableInstructionCache, CODE, READONLY ArmEnableInstructionCache ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) @@ -169,6 +177,7 @@ ArmEnableInstructionCache isb bx LR + AREA s_ArmDisableInstructionCache, CODE, READONLY ArmDisableInstructionCache ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) @@ -176,14 +185,16 @@ ArmDisableInstructionCache mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data) isb bx LR - + + AREA s_ArmEnableSWPInstruction, CODE, READONLY ArmEnableSWPInstruction mrc p15, 0, r0, c1, c0, 0 orr r0, r0, #0x00000400 mcr p15, 0, r0, c1, c0, 0 isb bx LR - + + AREA s_ArmEnableBranchPrediction, CODE, READONLY ArmEnableBranchPrediction mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data) orr r0, r0, #0x00000800 ; @@ -191,7 +202,8 @@ ArmEnableBranchPrediction dsb isb bx LR - + + AREA s_ArmDisableBranchPrediction, CODE, READONLY ArmDisableBranchPrediction mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data) bic r0, r0, #0x00000800 ; @@ -199,21 +211,24 @@ ArmDisableBranchPrediction dsb isb bx LR - + + AREA s_ArmSetLowVectors, CODE, READONLY ArmSetLowVectors mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data) bic r0, r0, #0x00002000 ; clear V bit mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data) isb bx LR - + + AREA s_ArmSetHighVectors, CODE, READONLY ArmSetHighVectors mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data) orr r0, r0, #0x00002000 ; clear V bit mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data) isb bx LR - + + AREA s_ArmV7AllDataCachesOperation, CODE, READONLY ArmV7AllDataCachesOperation stmfd SP!,{r4-r12, LR} mov R1, R0 ; Save Function call in R1 @@ -262,7 +277,8 @@ Finished dsb ldmfd SP!, {r4-r12, lr} bx LR - + + AREA s_ArmV7PerformPoUDataCacheOperation, CODE, READONLY ArmV7PerformPoUDataCacheOperation stmfd SP!,{r4-r12, LR} mov R1, R0 ; Save Function call in R1 @@ -311,25 +327,30 @@ Finished2 dsb ldmfd SP!, {r4-r12, lr} bx LR - + + AREA s_ArmDataMemoryBarrier, CODE, READONLY ArmDataMemoryBarrier dmb bx LR + AREA s_ArmDataSyncronizationBarrier, CODE, READONLY ArmDataSyncronizationBarrier ArmDrainWriteBuffer dsb bx LR + AREA s_ArmInstructionSynchronizationBarrier, CODE, READONLY ArmInstructionSynchronizationBarrier isb bx LR - + + AREA s_ArmReadVBar, CODE, READONLY ArmReadVBar // Set the Address of the Vector Table in the VBAR register mrc p15, 0, r0, c12, c0, 0 bx lr - + + AREA s_ArmWriteVBar, CODE, READONLY ArmWriteVBar // Set the Address of the Vector Table in the VBAR register mcr p15, 0, r0, c12, c0, 0 @@ -339,7 +360,8 @@ ArmWriteVBar mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data) isb bx lr - + + AREA s_ArmEnableVFP, CODE, READONLY ArmEnableVFP // Read CPACR (Coprocessor Access Control Register) mrc p15, 0, r0, c1, c0, 2 @@ -352,38 +374,46 @@ ArmEnableVFP mov r0, #0x40000000 mcr p10,#0x7,r0,c8,c0,#0 bx lr - + + AREA s_ArmCallWFI, CODE, READONLY ArmCallWFI wfi bx lr - + + AREA s_ArmReadCbar, CODE, READONLY //Note: Return 0 in Uniprocessor implementation ArmReadCbar mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register bx lr - + + AREA s_ArmInvalidateInstructionAndDataTlb, CODE, READONLY ArmInvalidateInstructionAndDataTlb mcr p15, 0, r0, c8, c7, 0 ; Invalidate Inst TLB and Data TLB dsb bx lr - + + AREA s_ArmReadMpidr, CODE, READONLY ArmReadMpidr mrc p15, 0, r0, c0, c0, 5 ; read MPIDR bx lr - + + AREA s_ArmReadTpidrurw, CODE, READONLY ArmReadTpidrurw mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW bx lr - + + AREA s_ArmWriteTpidrurw, CODE, READONLY ArmWriteTpidrurw mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW bx lr - + + AREA s_ArmIsArchTimerImplemented, CODE, READONLY ArmIsArchTimerImplemented mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 and r0, r0, #0x000F0000 bx lr - + + AREA s_ArmReadIdPfr1, CODE, READONLY ArmReadIdPfr1 mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register bx lr diff --git a/edk2/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm b/edk2/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm index fd0f332..ff6a3ff 100644 --- a/edk2/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm +++ b/edk2/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm @@ -48,34 +48,38 @@ EXPORT ArmCallSEV EXPORT ArmReadSctlr - AREA ArmLibSupport, CODE, READONLY - + AREA s_Cp15IdCode, CODE, READONLY Cp15IdCode mrc p15,0,R0,c0,c0,0 bx LR - + + AREA s_Cp15CacheInfo, CODE, READONLY Cp15CacheInfo mrc p15,0,R0,c0,c0,1 bx LR - + + AREA s_ArmGetInterruptState, CODE, READONLY ArmGetInterruptState mrs R0,CPSR tst R0,#0x80 // Check if IRQ is enabled. moveq R0,#1 movne R0,#0 bx LR - + + AREA s_ArmGetFiqState, CODE, READONLY ArmGetFiqState mrs R0,CPSR tst R0,#0x40 // Check if FIQ is enabled. moveq R0,#1 movne R0,#0 bx LR - + + AREA s_ArmSetDomainAccessControl, CODE, READONLY ArmSetDomainAccessControl mcr p15,0,r0,c3,c0,0 bx lr - + + AREA s_CPSRMaskInsert, CODE, READONLY CPSRMaskInsert // on entry, r0 is the mask and r1 is the field to insert stmfd sp!, {r4-r12, lr} // save all the banked registers mov r3, sp // copy the stack pointer into a non-banked register @@ -88,40 +92,48 @@ CPSRMaskInsert // on entry, r0 is the mask and r1 is the field to insert mov sp, r3 // restore stack pointer ldmfd sp!, {r4-r12, lr} // restore registers bx lr // return (hopefully thumb-safe!) // return (hopefully thumb-safe!) - + + AREA s_CPSRRead, CODE, READONLY CPSRRead mrs r0, cpsr bx lr - + + AREA s_ArmReadCpacr, CODE, READONLY ArmReadCpacr mrc p15, 0, r0, c1, c0, 2 bx lr - + + AREA s_ArmWriteCpacr, CODE, READONLY ArmWriteCpacr mcr p15, 0, r0, c1, c0, 2 isb bx lr - + + AREA s_ArmWriteAuxCr, CODE, READONLY ArmWriteAuxCr mcr p15, 0, r0, c1, c0, 1 bx lr - + + AREA s_ArmReadAuxCr, CODE, READONLY ArmReadAuxCr mrc p15, 0, r0, c1, c0, 1 bx lr - + + AREA s_ArmSetTTBR0, CODE, READONLY ArmSetTTBR0 mcr p15,0,r0,c2,c0,0 isb bx lr - + + AREA s_ArmGetTTBR0BaseAddress, CODE, READONLY ArmGetTTBR0BaseAddress mrc p15,0,r0,c2,c0,0 LoadConstantToReg(0xFFFFC000, r1) and r0, r0, r1 isb bx lr - + + AREA s_ArmUpdateTranslationTableEntry, CODE, READONLY // //VOID //ArmUpdateTranslationTableEntry ( @@ -136,7 +148,8 @@ ArmUpdateTranslationTableEntry dsb isb bx lr - + + AREA s_ArmInvalidateTlb, CODE, READONLY ArmInvalidateTlb mov r0,#0 mcr p15,0,r0,c8,c7,0 @@ -144,39 +157,48 @@ ArmInvalidateTlb dsb isb bx lr - + + AREA s_ArmReadNsacr, CODE, READONLY ArmReadNsacr mrc p15, 0, r0, c1, c1, 2 bx lr - + + AREA s_ArmWriteNsacr, CODE, READONLY ArmWriteNsacr mcr p15, 0, r0, c1, c1, 2 bx lr - + + AREA s_ArmReadScr, CODE, READONLY ArmReadScr mrc p15, 0, r0, c1, c1, 0 bx lr - + + AREA s_ArmWriteScr, CODE, READONLY ArmWriteScr mcr p15, 0, r0, c1, c1, 0 bx lr - + + AREA s_ArmReadMVBar, CODE, READONLY ArmReadMVBar mrc p15, 0, r0, c12, c0, 1 bx lr - + + AREA s_ArmWriteMVBar, CODE, READONLY ArmWriteMVBar mcr p15, 0, r0, c12, c0, 1 bx lr + AREA s_ArmCallWFE, CODE, READONLY ArmCallWFE wfe blx lr - + + AREA s_ArmCallSEV, CODE, READONLY ArmCallSEV sev blx lr - + + AREA s_ArmReadSctlr, CODE, READONLY ArmReadSctlr mrc p15, 0, R0, c1, c0, 0 // Read SCTLR into R0 (Read control register configuration data) bx lr -- 1.7.11.msysgit.1