Index: Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSpi.h
===================================================================
--- Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSpi.h	(revision 17548)
+++ Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSpi.h	(working copy)
@@ -1,6 +1,6 @@
 /**
 
-Copyright (c) 2011  - 2014, Intel Corporation. All rights reserved
+Copyright (c) 2011  - 2015, Intel Corporation. All rights reserved
 
   This program and the accompanying materials are licensed and made available under
   the terms and conditions of the BSD License that accompanies this distribution.
@@ -62,6 +62,12 @@
 #define B_PCH_SPI_PR0_RPE                    BIT15 // Read Protection Enable
 #define B_PCH_SPI_PR0_PRB_MASK               0x00001FFF // Protected Range Base Mask, [12:0] here represents base limit of address [24:12]
 
+#define R_PCH_SPI_PR1                        0x78  // Protected Region 1 Register
+#define B_PCH_SPI_PR1_WPE                    BIT31 // Write Protection Enable
+#define B_PCH_SPI_PR1_PRL_MASK               0x1FFF0000 // Protected Range Limit Mask, [28:16] here represents upper limit of address [24:12]
+#define B_PCH_SPI_PR1_RPE                    BIT15 // Read Protection Enable
+#define B_PCH_SPI_PR1_PRB_MASK               0x00001FFF // Protected Range Base Mask, [12:0] here represents base limit of address [24:12]
+
 #define R_PCH_SPI_PREOP                      0x94  // Prefix Opcode Configuration Register (16 bits)
 #define B_PCH_SPI_PREOP1_MASK                0xFF00 // Prefix Opcode 1 Mask
 #define B_PCH_SPI_PREOP0_MASK                0x00FF // Prefix Opcode 0 Mask
Index: Vlv2TbltDevicePkg/PlatformDxe/Platform.c
===================================================================
--- Vlv2TbltDevicePkg/PlatformDxe/Platform.c	(revision 17548)
+++ Vlv2TbltDevicePkg/PlatformDxe/Platform.c	(working copy)
@@ -353,12 +353,23 @@
 {
 
   UINTN                             mPciD31F0RegBase;
-  UINTN                             BiosFlaLower = 0;
-  UINTN                             BiosFlaLimit = 0x7fffff;
+  UINTN                             BiosFlaLower0;
+  UINTN                             BiosFlaLimit0;
+  UINTN                             BiosFlaLower1;
+  UINTN                             BiosFlaLimit1;  
+  
 
-  BiosFlaLower = PcdGet32(PcdFlashMicroCodeAddress)-PcdGet32(PcdFlashAreaBaseAddress);
+  BiosFlaLower0 = PcdGet32(PcdFlashMicroCodeAddress)-PcdGet32(PcdFlashAreaBaseAddress);
+  BiosFlaLimit0 = PcdGet32(PcdFlashMicroCodeSize)-1;  
+  #ifdef MINNOW2_FSP_BUILD
+  BiosFlaLower1 = PcdGet32(PcdFlashFvFspBase)-PcdGet32(PcdFlashAreaBaseAddress);
+  BiosFlaLimit1 = (PcdGet32(PcdFlashFvRecoveryBase)-PcdGet32(PcdFlashFvFspBase)+PcdGet32(PcdFlashFvRecoverySize))-1;
+  #else
+  BiosFlaLower1 = PcdGet32(PcdFlashFvMainBase)-PcdGet32(PcdFlashAreaBaseAddress);
+  BiosFlaLimit1 = (PcdGet32(PcdFlashFvRecoveryBase)-PcdGet32(PcdFlashFvMainBase)+PcdGet32(PcdFlashFvRecoverySize))-1;
+  #endif
 
-
+  
   mPciD31F0RegBase = MmPciAddress (0,
                          DEFAULT_PCI_BUS_NUMBER_PCH,
                          PCI_DEVICE_NUMBER_PCH_LPC,
@@ -391,7 +402,7 @@
   //
   MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR0),
     B_PCH_SPI_PR0_RPE|B_PCH_SPI_PR0_WPE|\
-    (B_PCH_SPI_PR0_PRB_MASK&(BiosFlaLower>>12))|(B_PCH_SPI_PR0_PRL_MASK&(BiosFlaLimit>>12)<<16));
+    (B_PCH_SPI_PR0_PRB_MASK&(BiosFlaLower0>>12))|(B_PCH_SPI_PR0_PRL_MASK&(BiosFlaLimit0>>12)<<16));
 
   //
   //Lock down PR0
@@ -405,6 +416,25 @@
     DEBUG((EFI_D_ERROR, "Failed to lock down PR0.\n"));
   }
 
+  //
+  //Set PR1
+  //
+
+  MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR1),
+    B_PCH_SPI_PR1_RPE|B_PCH_SPI_PR1_WPE|\
+    (B_PCH_SPI_PR1_PRB_MASK&(BiosFlaLower1>>12))|(B_PCH_SPI_PR1_PRL_MASK&(BiosFlaLimit1>>12)<<16));
+
+  //
+  //Lock down PR1
+  //
+  MmioOr16 ((UINTN) (SpiBase + R_PCH_SPI_HSFS), (UINT16) (B_PCH_SPI_HSFS_FLOCKDN));
+
+  //
+  // Verify if it's really locked.
+  //
+  if ((MmioRead16 (SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) == 0) {
+    DEBUG((EFI_D_ERROR, "Failed to lock down PR1.\n"));
+  }
   return;
 
 }
@@ -690,7 +720,7 @@
              &mReadyToBootEvent
              );
   //
-  // Create a ReadyToBoot Event to run enable PR0 and lock down
+  // Create a ReadyToBoot Event to run enable PR0/PR1 and lock down,unlock variable region
   //
   if(mSystemConfiguration.SpiRwProtect==1) {
     Status = EfiCreateEventReadyToBootEx (
Index: Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.inf
===================================================================
--- Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.inf	(revision 17548)
+++ Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.inf	(working copy)
@@ -62,6 +62,7 @@
   Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
   SecurityPkg/SecurityPkg.dec
   CryptoPkg/CryptoPkg.dec
+  IntelFspWrapperPkg/IntelFspWrapperPkg.dec
 
 [LibraryClasses]
   BaseLib
@@ -133,7 +134,13 @@
   gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
   gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress
   gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeAddress
+  gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeSize
   gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdFastPS2Detection
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoverySize
+  gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase
+  
 
 [Depex]
   gEfiPciRootBridgeIoProtocolGuid     AND