https://gcc.gnu.org/bugzilla/show_bug.cgi?id=124804
--- Comment #17 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
For that, in IRA dump we have
(insn 66 62 69 4 (set (reg:OO 181 [ _110 ])
(mem:OO (plus:DI (reg/f:DI 253 [ _255 ])
(reg:DI 119 [ ivtmp.80 ])) [0 MEM[(__vector_pair *)_255 +
ivtmp.80_3 * 1]+0 S32 A128])) "sbq.i":11:10 2209 {*movoo}
(expr_list:REG_EQUIV (mem:OO (plus:DI (reg/f:DI 253 [ _255 ])
(reg:DI 119 [ ivtmp.80 ])) [0 MEM[(__vector_pair *)_255 +
ivtmp.80_3 * 1]+0 S32 A128])
(nil)))
...
(insn 86 85 87 4 (set (reg:XO 200 [ _129 ])
(unspec:XO [
(reg:XO 196 [ _125 ])
(subreg:V16QI (reg:OO 181 [ _110 ]) 16)
(subreg:V16QI (reg:OO 209 [ _138 ]) 16)
] UNSPEC_MMA_XVBF16GER2PP)) 2232 {mma_xvbf16ger2pp}
(expr_list:REG_DEAD (reg:XO 196 [ _125 ])
(nil)))
(...
(insn 90 89 91 4 (set (reg:XO 204 [ temp0$128 ])
(unspec:XO [
(reg:XO 200 [ _129 ])
(subreg:V16QI (reg:OO 181 [ _110 ]) 0)
(subreg:V16QI (reg:OO 209 [ _138 ]) 0)
] UNSPEC_MMA_XVBF16GER2PP)) 2232 {mma_xvbf16ger2pp}
(expr_list:REG_DEAD (reg:XO 200 [ _129 ])
(expr_list:REG_DEAD (reg:OO 181 [ _110 ])
(nil))))
(in both ira dumps, the relative scheduling is the same, but there are
different insns in between).
reload dump with -fno-schedule-insns has then
(insn 66 62 69 5 (set (reg:OO 76 12 [orig:181 _110 ] [181])
(mem:OO (plus:DI (reg/f:DI 30 30 [orig:253 _255 ] [253])
(reg:DI 2 2 [orig:119 ivtmp.80 ] [119])) [0 MEM[(__vector_pair
*)_255 + ivtmp.80_3 * 1]+0 S32 A128])) "sbq.i":11:10 2209 {*movoo}
(expr_list:REG_EQUIV (mem:OO (plus:DI (reg/f:DI 30 30 [orig:253 _255 ]
[253])
(reg:DI 2 2 [orig:119 ivtmp.80 ] [119])) [0 MEM[(__vector_pair
*)_255 + ivtmp.80_3 * 1]+0 S32 A128])
(nil)))
...
(insn 86 85 87 5 (set (reg:XO 52 20 [orig:200 _129 ] [200])
(unspec:XO [
(reg:XO 52 20 [orig:200 _129 ] [200])
(reg:V16QI 77 13 [ _110+16 ])
(reg:V16QI 81 17 [ _138+16 ])
] UNSPEC_MMA_XVBF16GER2PP)) 2232 {mma_xvbf16ger2pp}
(nil))
...
(insn 90 89 91 5 (set (reg:XO 52 20 [orig:204 temp0$128 ] [204])
(unspec:XO [
(reg:XO 52 20 [orig:204 temp0$128 ] [204])
(reg:V16QI 76 12 [orig:181 _110 ] [181])
(reg:V16QI 80 16 [orig:209 _138 ] [209])
] UNSPEC_MMA_XVBF16GER2PP)) 2232 {mma_xvbf16ger2pp}
(nil))
and without that option insn 66 is gone, and
(insn 229 85 230 5 (set (reg:OO 64 0 [282])
(mem:OO (plus:DI (reg/f:DI 28 28 [orig:253 _255 ] [253])
(reg:DI 2 2 [orig:119 ivtmp.80 ] [119])) [0 MEM[(__vector_pair
*)_255 + ivtmp.80_3 * 1]+0 S32 A128])) 2209 {*movoo}
(nil))
(insn 230 229 86 5 (set (reg:V16QI 64 0 [283])
(reg:V16QI 65 1 [+16 ])) 1187 {vsx_movv16qi_64bit}
(nil))
(insn 86 230 233 5 (set (reg:XO 52 20 [orig:200 _129 ] [200])
(unspec:XO [
(reg:XO 52 20 [orig:200 _129 ] [200])
(reg:V16QI 64 0 [283])
(reg:V16QI 95 31 [ _138+16 ])
] UNSPEC_MMA_XVBF16GER2PP)) 2232 {mma_xvbf16ger2pp}
(nil))
...
(insn 255 89 90 5 (set (reg:V16QI 64 0 [299])
(mem:V16QI (plus:DI (reg/f:DI 28 28 [orig:253 _255 ] [253])
(reg:DI 2 2 [orig:119 ivtmp.80 ] [119])) [0 MEM[(__vector_pair
*)_255 + ivtmp.80_3 * 1]+0 S16 A128])) 1187 {vsx_movv16qi_64bit}
(nil))
(insn 90 255 258 5 (set (reg:XO 52 20 [orig:204 temp0$128 ] [204])
(unspec:XO [
(reg:XO 52 20 [orig:204 temp0$128 ] [204])
(reg:V16QI 64 0 [299])
(reg:V16QI 94 30 [orig:209 _138 ] [209])
] UNSPEC_MMA_XVBF16GER2PP)) 2232 {mma_xvbf16ger2pp}
(nil))
