https://gcc.gnu.org/bugzilla/show_bug.cgi?id=124804
--- Comment #24 from Jakub Jelinek <jakub at gcc dot gnu.org> --- The ISA 3.1 manual says: When Big-Endian byte ordering is employed, the contents of the octword in storage at address EA are placed into load_data in such an order that; – the contents of the byte in storage at address EA are placed into byte 0 of load_data, – the contents of the byte in storage at address EA+1 are placed into byte 1 of load_data, and so forth until – the contents of the byte in storage at address EA+31 are placed into byte 31 of load_data. When Little-Endian byte ordering is employed, the contents of the octword in storage at address EA are placed into load_data in such an order that; – the contents of the byte in storage at address EA are placed into byte 31 of load_data, – the contents of the byte in storage at address EA+1 are placed into byte 30 of load_data, and so forth until – the contents of the byte in storage at address EA+31 are placed into byte 0 of load_data. Bits 0-127 of load_data are placed into VSR[XTp]. Bits 128-255 of load_data is placed into VSR[XTp+1].
