https://gcc.gnu.org/bugzilla/show_bug.cgi?id=124804
Jakub Jelinek <jakub at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |NEW
Ever confirmed|0 |1
Last reconfirmed| |2026-04-10
--- Comment #28 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Note, if trying to change ppc64le behavior of subreg folding on OO/XOmode VSX
regs, so that they match the memory ordering (i.e. that
(subreg:V16QI (reg:OO N) 0) folds to (reg:V16QI N + 1) rather than (reg:V16QI
N)
and
(subreg:V16QI (reg:OO N) 16) folds to (reg:V16QI N) rather than (reg:V16QI N +
1)
etc.) is too complicated, perhaps yet another possibility would be to change
the RTL representation of OOmode/XOmode memory loads and stores for little
endian, so that it reflects the PDP-endian-ish behavior by permuting the
128-bit parts.
Though not sure if LRA won't be upset by that and expects simple movoo or movxo
to be really (set (regmem:OO) (regmem:OO)) rather than something that permutes
the 128-bit parts.
