https://gcc.gnu.org/bugzilla/show_bug.cgi?id=124894
Richard Biener <rguenth at gcc dot gnu.org> changed:
What |Removed |Added
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CC| |rguenth at gcc dot gnu.org
--- Comment #4 from Richard Biener <rguenth at gcc dot gnu.org> ---
REG_EQUAL with MEM are fishy, I believe we nowhere check for aliasing when we
optimize an insn with such a REG_EQUAL against stores, do we? Does sched1
care for example? combine does not:
/* Try this insn with each REG_EQUAL note it links back to. */
FOR_EACH_LOG_LINK (links, insn)
{
rtx set, note;
rtx_insn *temp = links->insn;
if ((set = single_set (temp)) != 0
&& (note = find_reg_equal_equiv_note (temp)) != 0
&& (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
&& ! side_effects_p (SET_SRC (set))
/* Avoid using a register that may already been marked
dead by an earlier instruction. */
&& ! unmentioned_reg_p (note, SET_SRC (set))
&& (GET_MODE (note) == VOIDmode
? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
: (GET_MODE (SET_DEST (set)) == GET_MODE (note)
&& (GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
|| (GET_MODE (XEXP (SET_DEST (set), 0))
== GET_MODE (note))))))
{
/* Temporarily replace the set's source with the
contents of the REG_EQUAL note. The insn will
be deleted or recognized by try_combine. */
