https://gcc.gnu.org/g:4da7ba86179ffe27956c0ae0191ad9c4a7724443
commit r16-2202-g4da7ba86179ffe27956c0ae0191ad9c4a7724443
Author: Kyrylo Tkachov <ktkac...@nvidia.com>
Date: Thu Jul 3 08:58:19 2025 -0700
aarch64: Use EOR3 for 64-bit vector modes
Similar to the BCAX patch, we can also use EOR3 for 64-bit modes,
just by adjusting the mode iterator used.
Thus for input:
uint32x2_t
bcax_s (uint32x2_t a, uint32x2_t b, uint32x2_t c)
{
return EOR3 (a, b, c);
}
we now generate:
bcax_s:
eor3 v0.16b, v0.16b, v1.16b, v2.16b
ret
instead of:
bcax_s:
eor v1.8b, v1.8b, v2.8b
eor v0.8b, v1.8b, v0.8b
ret
Signed-off-by: Kyrylo Tkachov <ktkac...@nvidia.com>
gcc/
* config/aarch64/aarch64-simd.md (eor3q<mode>4): Use VDQ_I mode
iterator.
gcc/testsuite/
* gcc.target/aarch64/simd/eor3_d.c: New test.
Diff:
---
gcc/config/aarch64/aarch64-simd.md | 12 ++++++------
gcc/testsuite/gcc.target/aarch64/simd/eor3_d.c | 15 +++++++++++++++
2 files changed, 21 insertions(+), 6 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-simd.md
b/gcc/config/aarch64/aarch64-simd.md
index 879b1a27bb19..4493e55603d1 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -9180,12 +9180,12 @@
;; sha3
(define_insn "eor3q<mode>4"
- [(set (match_operand:VQ_I 0 "register_operand" "=w")
- (xor:VQ_I
- (xor:VQ_I
- (match_operand:VQ_I 2 "register_operand" "w")
- (match_operand:VQ_I 3 "register_operand" "w"))
- (match_operand:VQ_I 1 "register_operand" "w")))]
+ [(set (match_operand:VDQ_I 0 "register_operand" "=w")
+ (xor:VDQ_I
+ (xor:VDQ_I
+ (match_operand:VDQ_I 2 "register_operand" "w")
+ (match_operand:VDQ_I 3 "register_operand" "w"))
+ (match_operand:VDQ_I 1 "register_operand" "w")))]
"TARGET_SHA3"
"eor3\\t%0.16b, %1.16b, %2.16b, %3.16b"
[(set_attr "type" "crypto_sha3")]
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/eor3_d.c
b/gcc/testsuite/gcc.target/aarch64/simd/eor3_d.c
new file mode 100644
index 000000000000..7f2b2b422685
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/eor3_d.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include <arm_neon.h>
+
+#pragma GCC target "+sha3"
+
+#define EOR3(x,y,z) ((x) ^ (y) ^ (z))
+
+uint32x2_t bcax_s (uint32x2_t a, uint32x2_t b, uint32x2_t c) { return EOR3 (a,
b, c); }
+uint16x4_t bcax_h (uint16x4_t a, uint16x4_t b, uint16x4_t c) { return EOR3 (a,
b, c); }
+uint8x8_t bcax_b (uint8x8_t a, uint8x8_t b, uint8x8_t c) { return EOR3 (a, b,
c); }
+
+/* { dg-final { scan-assembler-times {eor3\tv0.16b, v[0-9]+.16b, v[0-9]+.16b,
v[0-9]+.16b} 3 } } */
+
