Index: gcc/config/m32c/addsub.md
===================================================================
--- gcc/config/m32c/addsub.md	(revision 211088)
+++ gcc/config/m32c/addsub.md	(working copy)
@@ -81,7 +81,7 @@
 (define_insn "addsi3_1"
   [(set (match_operand:SI 0 "mra_operand" "=RsiSd,??Rmm,RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
         (plus:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
-                 (match_operand 2 "mrai_operand" "IU2,IU2,i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
+                 (match_operand:SI 2 "mrai_operand" "IU2,IU2,i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
   "TARGET_A16"
   "*
   
Index: gcc/config/m32c/bitops.md
===================================================================
--- gcc/config/m32c/bitops.md	(revision 211088)
+++ gcc/config/m32c/bitops.md	(working copy)
@@ -82,7 +82,7 @@
 (define_insn "andqi3_16"
   [(set (match_operand:QI 0 "mra_operand" "=Sp,Rqi,RhlSd,RhlSd,??Rmm,??Rmm")
 	(and:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
-		(match_operand 2 "mrai_operand" "Imb,Imb,iRhlSd,?Rmm,iRhlSd,?Rmm")))]
+		(match_operand:QI 2 "mrai_operand" "Imb,Imb,iRhlSd,?Rmm,iRhlSd,?Rmm")))]
   "TARGET_A16"
   "@
    bclr\t%B2,%0
@@ -178,7 +178,7 @@
 (define_insn "andqi3_24"
   [(set (match_operand:QI 0 "mra_operand" "=Sd,Rqi,RhlSd,RhlSd,??Rmm,??Rmm")
 	(and:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
-		(match_operand 2 "mrai_operand" "Imb,Imb,iRhlSd,?Rmm,iRhlSd,?Rmm")))]
+		(match_operand:QI 2 "mrai_operand" "Imb,Imb,iRhlSd,?Rmm,iRhlSd,?Rmm")))]
   "TARGET_A24"
   "@
    bclr\t%B2,%0
Index: gcc/config/m32c/m32c.c
===================================================================
--- gcc/config/m32c/m32c.c	(revision 211088)
+++ gcc/config/m32c/m32c.c	(working copy)
@@ -117,6 +117,7 @@ static bool m32c_get_pragma_address (const char *v
 #define DEBUG1 1
 
 #if DEBUG0
+#include "print-tree.h"
 /* This is needed by some of the commented-out debug statements
    below.  */
 static char const *class_names[LIM_REG_CLASSES] = REG_CLASS_NAMES;
@@ -260,7 +261,6 @@ encode_pattern_1 (rtx x)
       fprintf (stderr, "can't encode pattern %s\n",
 	       GET_RTX_NAME (GET_CODE (x)));
       debug_rtx (x);
-      gcc_unreachable ();
 #endif
       break;
     }
@@ -652,8 +652,6 @@ m32c_regno_ok_for_base_p (int regno)
   return 0;
 }
 
-#define DEBUG_RELOAD 0
-
 /* Implements TARGET_PREFERRED_RELOAD_CLASS.  In general, prefer general
    registers of the appropriate size.  */
 
@@ -665,7 +663,7 @@ m32c_preferred_reload_class (rtx x, reg_class_t rc
 {
   reg_class_t newclass = rclass;
 
-#if DEBUG_RELOAD
+#if DEBUG0
   fprintf (stderr, "\npreferred_reload_class for %s is ",
 	   class_names[rclass]);
 #endif
@@ -696,7 +694,7 @@ m32c_preferred_reload_class (rtx x, reg_class_t rc
   if (GET_MODE (x) == QImode)
     rclass = reduce_class (rclass, HL_REGS, rclass);
 
-#if DEBUG_RELOAD
+#if DEBUG0
   fprintf (stderr, "%s\n", class_names[rclass]);
   debug_rtx (x);
 
@@ -725,7 +723,7 @@ m32c_preferred_output_reload_class (rtx x, reg_cla
 int
 m32c_limit_reload_class (enum machine_mode mode, int rclass)
 {
-#if DEBUG_RELOAD
+#if DEBUG0
   fprintf (stderr, "limit_reload_class for %s: %s ->",
 	   mode_name[mode], class_names[rclass]);
 #endif
@@ -740,7 +738,7 @@ m32c_limit_reload_class (enum machine_mode mode, i
   if (rclass != A_REGS)
     rclass = reduce_class (rclass, DI_REGS, rclass);
 
-#if DEBUG_RELOAD
+#if DEBUG0
   fprintf (stderr, " %s\n", class_names[rclass]);
 #endif
   return rclass;
@@ -1341,7 +1339,7 @@ m32c_function_arg (cumulative_args_t ca_v,
 #if DEBUG0
   fprintf (stderr, "func_arg %d (%s, %d)\n",
 	   ca->parm_num, mode_name[mode], named);
-  debug_tree (type);
+  debug_tree ((tree)type);
 #endif
 
   if (mode == VOIDmode)
@@ -1925,6 +1923,14 @@ m32c_legitimize_reload_address (rtx * x,
       return 1;
     }
 
+  if (TARGET_A24 && GET_MODE (*x) == PSImode)
+    {
+      push_reload (*x, NULL_RTX, x, NULL,
+		   A_REGS, PSImode, VOIDmode, 0, 0, opnum,
+		   (enum reload_type) type);
+      return 1;
+    }
+
   return 0;
 }
 
Index: gcc/config/m32c/mov.md
===================================================================
--- gcc/config/m32c/mov.md	(revision 211088)
+++ gcc/config/m32c/mov.md	(working copy)
@@ -162,9 +162,9 @@
 ; immediate double data to a memory location.
 (define_peephole2
   [(set (match_operand:HI 0 "memory_operand" "")
-        (match_operand 1 "const_int_operand" ""))
+        (match_operand:HI 1 "const_int_operand" ""))
    (set (match_operand:HI 2 "memory_operand" "")
-        (match_operand 3 "const_int_operand" ""))]
+        (match_operand:HI 3 "const_int_operand" ""))]
    "TARGET_A24 && m32c_immd_dbl_mov (operands, HImode)"
    [(set (match_dup 4) (match_dup 5))]
    ""
@@ -213,7 +213,7 @@
 ; don't match.
 (define_insn "push_a01_l"
   [(set (mem:SI (pre_dec:PSI (reg:PSI SP_REGNO)))
-	(match_operand 0 "a_operand" "Raa"))]
+	(match_operand:SI 0 "a_operand" "Raa"))]
   ""
   "push.l\t%0"
   [(set_attr "flags" "n")]