From fb81b148541e7d7f095022900bf2763c9ab52727 Mon Sep 17 00:00:00 2001 From: "julia.koval" Date: Mon, 20 Feb 2017 14:25:53 +0300 Subject: [PATCH 4/4] GF2P8MULB instruction --- gcc/config/i386/gfniintrin.h | 75 +++++++++++++++++++++ gcc/config/i386/i386-builtin-types.def | 1 + gcc/config/i386/i386-builtin.def | 6 ++ gcc/config/i386/i386.c | 1 + gcc/config/i386/sse.md | 17 +++++ .../gcc.target/i386/avx512f-gf2p8mulb-2.c | 76 ++++++++++++++++++++++ .../gcc.target/i386/avx512vl-gf2p8mulb-2.c | 17 +++++ gcc/testsuite/gcc.target/i386/gfni-1.c | 6 ++ gcc/testsuite/gcc.target/i386/gfni-2.c | 12 ++++ gcc/testsuite/gcc.target/i386/gfni-3.c | 4 ++ gcc/testsuite/gcc.target/i386/gfni-4.c | 2 + 11 files changed, 217 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-gf2p8mulb-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-gf2p8mulb-2.c diff --git a/gcc/config/i386/gfniintrin.h b/gcc/config/i386/gfniintrin.h index 9ddd2e0..94b1d90 100644 --- a/gcc/config/i386/gfniintrin.h +++ b/gcc/config/i386/gfniintrin.h @@ -34,6 +34,14 @@ #define __DISABLE_GFNI__ #endif /* __GFNI__ */ +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_gf2p8mul_epi8 (__m128i __A, __m128i __B) +{ + return (__m128i) __builtin_ia32_vgf2p8mulb_v16qi((__v16qi) __A, + (__v16qi) __B); +} + #ifdef __OPTIMIZE__ extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) @@ -71,6 +79,14 @@ _mm_gf2p8affine_epi64_epi8 (__m128i __A, __m128i __B, const int __C) #define __DISABLE_GFNIAVX__ #endif /* __GFNIAVX__ */ +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_gf2p8mul_epi8 (__m256i __A, __m256i __B) +{ + return (__m256i) __builtin_ia32_vgf2p8mulb_v32qi ((__v32qi) __A, + (__v32qi) __B); +} + #ifdef __OPTIMIZE__ extern __inline __m256i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) @@ -109,6 +125,23 @@ _mm256_gf2p8affine_epi64_epi8 (__m256i __A, __m256i __B, const int __C) #define __DISABLE_GFNIAVX512VL__ #endif /* __GFNIAVX512VL__ */ +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask_gf2p8mul_epi8 (__m128i __A, __mmask16 __B, __m128i __C, __m128i __D) +{ + return (__m128i) __builtin_ia32_vgf2p8mulb_v16qi_mask ((__v16qi) __C, + (__v16qi) __D, + (__v16qi)__A, __B); +} + +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_maskz_gf2p8mul_epi8 (__mmask16 __A, __m128i __B, __m128i __C) +{ + return (__m128i) __builtin_ia32_vgf2p8mulb_v16qi_mask ((__v16qi) __B, + (__v16qi) __C, (__v16qi) _mm_setzero_si128 (), __A); +} + #ifdef __OPTIMIZE__ extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) @@ -180,6 +213,24 @@ _mm_maskz_gf2p8affine_epi64_epi8 (__mmask16 __A, __m128i __B, __m128i __C, #define __DISABLE_GFNIAVX512VLBW__ #endif /* __GFNIAVX512VLBW__ */ +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_gf2p8mul_epi8 (__m256i __A, __mmask32 __B, __m256i __C, + __m256i __D) +{ + return (__m256i) __builtin_ia32_vgf2p8mulb_v32qi_mask ((__v32qi) __C, + (__v32qi) __D, + (__v32qi)__A, __B); +} + +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_gf2p8mul_epi8 (__mmask32 __A, __m256i __B, __m256i __C) +{ + return (__m256i) __builtin_ia32_vgf2p8mulb_v32qi_mask ((__v32qi) __B, + (__v32qi) __C, (__v32qi) _mm256_setzero_si256 (), __A); +} + #ifdef __OPTIMIZE__ extern __inline __m256i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) @@ -252,6 +303,30 @@ _mm256_maskz_gf2p8affine_epi64_epi8 (__mmask32 __A, __m256i __B, #define __DISABLE_GFNIAVX512FBW__ #endif /* __GFNIAVX512FBW__ */ +extern __inline __m512i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_gf2p8mul_epi8 (__m512i __A, __mmask64 __B, __m512i __C, + __m512i __D) +{ + return (__m512i) __builtin_ia32_vgf2p8mulb_v64qi_mask ((__v64qi) __C, + (__v64qi) __D, (__v64qi)__A, __B); +} + +extern __inline __m512i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_maskz_gf2p8mul_epi8 (__mmask64 __A, __m512i __B, __m512i __C) +{ + return (__m512i) __builtin_ia32_vgf2p8mulb_v64qi_mask ((__v64qi) __B, + (__v64qi) __C, (__v64qi) _mm512_setzero_si512 (), __A); +} +extern __inline __m512i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_gf2p8mul_epi8 (__m512i __A, __m512i __B) +{ + return (__m512i) __builtin_ia32_vgf2p8mulb_v64qi ((__v64qi) __A, + (__v64qi) __B); +} + #ifdef __OPTIMIZE__ extern __inline __m512i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def index f4508f4..a1b105e 100644 --- a/gcc/config/i386/i386-builtin-types.def +++ b/gcc/config/i386/i386-builtin-types.def @@ -1216,3 +1216,4 @@ DEF_FUNCTION_TYPE (V64QI, V64QI, V64QI, INT) DEF_FUNCTION_TYPE (V64QI, V64QI, V64QI, INT, V64QI, UDI) DEF_FUNCTION_TYPE (V32QI, V32QI, V32QI, INT, V32QI, USI) DEF_FUNCTION_TYPE (V16QI, V16QI, V16QI, INT, V16QI, UHI) +DEF_FUNCTION_TYPE (V64QI, V64QI, V64QI) diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index eee9d64..49221ab 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -2602,6 +2602,12 @@ BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8affineqb_v32qi, "__builtin_ia32_vgf2 BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8affineqb_v32qi_mask, "__builtin_ia32_vgf2p8affineqb_v32qi_mask", IX86_BUILTIN_VGF2P8AFFINEQB256MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT_V32QI_USI) BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8affineqb_v16qi, "__builtin_ia32_vgf2p8affineqb_v16qi", IX86_BUILTIN_VGF2P8AFFINEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT) BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8affineqb_v16qi_mask, "__builtin_ia32_vgf2p8affineqb_v16qi_mask", IX86_BUILTIN_VGF2P8AFFINEQB128MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT_V16QI_UHI) +BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8mulb_v64qi, "__builtin_ia32_vgf2p8mulb_v64qi", IX86_BUILTIN_VGF2P8MULB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) +BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8mulb_v64qi_mask, "__builtin_ia32_vgf2p8mulb_v64qi_mask", IX86_BUILTIN_VGF2P8MULB512MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI) +BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8mulb_v32qi, "__builtin_ia32_vgf2p8mulb_v32qi", IX86_BUILTIN_VGF2P8MULB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) +BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8mulb_v32qi_mask, "__builtin_ia32_vgf2p8mulb_v32qi_mask", IX86_BUILTIN_VGF2P8MULB256MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI) +BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8mulb_v16qi, "__builtin_ia32_vgf2p8mulb_v16qi", IX86_BUILTIN_VGF2P8MULB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) +BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8mulb_v16qi_mask, "__builtin_ia32_vgf2p8mulb_v16qi_mask", IX86_BUILTIN_VGF2P8MULB128MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI) BDESC_END (ARGS2, MPX) /* Builtins for MPX. */ diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 5a192e4..74ff6fb 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -33146,6 +33146,7 @@ ix86_expand_args_builtin (const struct builtin_description *d, case V1DI_FTYPE_V2SI_V2SI: case V32QI_FTYPE_V16HI_V16HI: case V16HI_FTYPE_V8SI_V8SI: + case V64QI_FTYPE_V64QI_V64QI: case V32QI_FTYPE_V32QI_V32QI: case V16HI_FTYPE_V32QI_V32QI: case V16HI_FTYPE_V16HI_V16HI: diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index fe583ed..0ce9074 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -161,6 +161,7 @@ ;; For GFNI support UNSPEC_GF2P8AFFINEINV UNSPEC_GF2P8AFFINE + UNSPEC_GF2P8MUL ]) (define_c_enum "unspecv" [ @@ -20206,3 +20207,19 @@ (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,maybe_evex,evex") (set_attr "mode" "")]) + +(define_insn "vgf2p8mulb_" + [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v") + (unspec:VI1_AVX512F [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v") + (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")] + UNSPEC_GF2P8MUL))] + "TARGET_GFNI" + "@ + gf2p8mulb\t{%2, %0| %0, %2} + vgf2p8mulb\t{%2, %1, %0| %0, %1, %2} + vgf2p8mulb\t{%2, %1, %0| %0, %1, %2}" + [(set_attr "isa" "noavx,avx,avx512bw") + (set_attr "prefix_data16" "1,*,*") + (set_attr "prefix_extra" "1") + (set_attr "prefix" "orig,maybe_evex,evex") + (set_attr "mode" "")]) diff --git a/gcc/testsuite/gcc.target/i386/avx512f-gf2p8mulb-2.c b/gcc/testsuite/gcc.target/i386/avx512f-gf2p8mulb-2.c new file mode 100644 index 0000000..08fc5b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-gf2p8mulb-2.c @@ -0,0 +1,76 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512f -mgfni -mavx512bw" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-require-effective-target gfni } */ + +#define AVX512F + +#define GFNI +#include "avx512f-helper.h" + +#define SIZE (AVX512F_LEN / 8) + +#include "avx512f-mask-type.h" + +static void +CALC (unsigned char *r, unsigned char *s1, unsigned char *s2) +{ + for (int i = 0; i < SIZE; i++) + { + unsigned short result = 0; + for (int bit = 0; bit < 8; bit++) + { + if ((s1[i] >> bit) & 1) + { + result ^= s2[i] << bit; + } + } + // Reduce result by x^8 + x^4 + x^3 + x + 1 + for (int bit = 14; bit > 7; bit--) + { + unsigned short p = 0x11B << (bit - 8); + if ((result >> bit) & 1) + result ^= p; + } + r[i] = result; + } +} + +void +TEST (void) +{ + int i; + UNION_TYPE (AVX512F_LEN, i_b) res1, res2, res3, src1, src2; + MASK_TYPE mask = MASK_VALUE; + unsigned char res_ref[SIZE]; + + for (i = 0; i < SIZE; i++) + { + src1.a[i] = 1 + i; + src2.a[i] = 2 + 2*i; + } + + for (i = 0; i < SIZE; i++) + { + res1.a[i] = DEFAULT_VALUE; + res2.a[i] = DEFAULT_VALUE; + res3.a[i] = DEFAULT_VALUE; + } + + CALC (res_ref, src1.a, src2.a); + + res1.x = INTRINSIC (_gf2p8mul_epi8) (src1.x, src2.x); + res2.x = INTRINSIC (_mask_gf2p8mul_epi8) (res2.x, mask, src1.x, src2.x); + res3.x = INTRINSIC (_maskz_gf2p8mul_epi8) (mask, src1.x, src2.x); + + if (UNION_CHECK (AVX512F_LEN, i_b) (res1, res_ref)) + abort (); + + MASK_MERGE (i_b) (res_ref, mask, SIZE); + if (UNION_CHECK (AVX512F_LEN, i_b) (res2, res_ref)) + abort (); + + MASK_ZERO (i_b) (res_ref, mask, SIZE); + if (UNION_CHECK (AVX512F_LEN, i_b) (res3, res_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-gf2p8mulb-2.c b/gcc/testsuite/gcc.target/i386/avx512vl-gf2p8mulb-2.c new file mode 100644 index 0000000..8215247 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-gf2p8mulb-2.c @@ -0,0 +1,17 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512bw -mavx512vl -mgfni" } */ +/* { dg-require-effective-target avx512vl } */ +/* { dg-require-effective-target avx512bw } */ +/* { dg-require-effective-target gfni } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512f-gf2p8mulb-2.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512f-gf2p8mulb-2.c" diff --git a/gcc/testsuite/gcc.target/i386/gfni-1.c b/gcc/testsuite/gcc.target/i386/gfni-1.c index 71e6db2..bf72ad0 100644 --- a/gcc/testsuite/gcc.target/i386/gfni-1.c +++ b/gcc/testsuite/gcc.target/i386/gfni-1.c @@ -6,6 +6,9 @@ /* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgf2p8mulb\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgf2p8mulb\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgf2p8mulb\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ #include @@ -21,4 +24,7 @@ avx512vl_test (void) x1 = _mm512_gf2p8affine_epi64_epi8(x1, x2, 3); x1 = _mm512_mask_gf2p8affine_epi64_epi8(x1, m64, x2, x1, 3); x1 = _mm512_maskz_gf2p8affine_epi64_epi8(m64, x1, x2, 3); + x1 = _mm512_gf2p8mul_epi8(x1, x2); + x1 = _mm512_mask_gf2p8mul_epi8(x1, m64, x2, x1); + x1 = _mm512_maskz_gf2p8mul_epi8(m64, x1, x2); } diff --git a/gcc/testsuite/gcc.target/i386/gfni-2.c b/gcc/testsuite/gcc.target/i386/gfni-2.c index 14764b5..413cb64 100644 --- a/gcc/testsuite/gcc.target/i386/gfni-2.c +++ b/gcc/testsuite/gcc.target/i386/gfni-2.c @@ -12,6 +12,12 @@ /* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgf2p8mulb\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgf2p8mulb\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgf2p8mulb\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgf2p8mulb\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgf2p8mulb\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgf2p8mulb\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ #include @@ -36,4 +42,10 @@ avx512vl_test (void) x5 = _mm_gf2p8affine_epi64_epi8(x5, x6, 3); x5 = _mm_mask_gf2p8affine_epi64_epi8(x5, m16, x6, x5, 3); x5 = _mm_maskz_gf2p8affine_epi64_epi8(m16, x5, x6, 3); + x3 = _mm256_gf2p8mul_epi8(x3, x4); + x3 = _mm256_mask_gf2p8mul_epi8(x3, m32, x4, x3); + x3 = _mm256_maskz_gf2p8mul_epi8(m32, x3, x4); + x5 = _mm_gf2p8mul_epi8(x5, x6); + x5 = _mm_mask_gf2p8mul_epi8(x5, m16, x6, x5); + x5 = _mm_maskz_gf2p8mul_epi8(m16, x5, x6); } diff --git a/gcc/testsuite/gcc.target/i386/gfni-3.c b/gcc/testsuite/gcc.target/i386/gfni-3.c index 3e39f4e..2beedc8 100644 --- a/gcc/testsuite/gcc.target/i386/gfni-3.c +++ b/gcc/testsuite/gcc.target/i386/gfni-3.c @@ -4,6 +4,8 @@ /* { dg-final { scan-assembler-times "vgf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgf2p8mulb\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgf2p8mulb\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ #include @@ -18,4 +20,6 @@ avx512vl_test (void) x5 = _mm_gf2p8affineinv_epi64_epi8(x5, x6, 3); x3 = _mm256_gf2p8affine_epi64_epi8(x3, x4, 3); x5 = _mm_gf2p8affine_epi64_epi8(x5, x6, 3); + x3 = _mm256_gf2p8mul_epi8(x3, x4); + x5 = _mm_gf2p8mul_epi8(x5, x6); } diff --git a/gcc/testsuite/gcc.target/i386/gfni-4.c b/gcc/testsuite/gcc.target/i386/gfni-4.c index 6103547..937ebc1 100644 --- a/gcc/testsuite/gcc.target/i386/gfni-4.c +++ b/gcc/testsuite/gcc.target/i386/gfni-4.c @@ -2,6 +2,7 @@ /* { dg-options "-mgfni -O2" } */ /* { dg-final { scan-assembler-times "gf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "gf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "gf2p8mulb\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ #include @@ -13,4 +14,5 @@ avx512vl_test (void) { x5 = _mm_gf2p8affineinv_epi64_epi8(x5, x6, 3); x5 = _mm_gf2p8affine_epi64_epi8(x5, x6, 3); + x5 = _mm_gf2p8mul_epi8(x5, x6); } -- 1.8.3.1