From 946f05b8b02cf590ab4d4aa06bfcbe4b7904ff3a Mon Sep 17 00:00:00 2001 From: "julia.koval" Date: Mon, 27 Feb 2017 22:42:13 +0300 Subject: [PATCH 1/5] VAES option --- gcc/common/config/i386/i386-common.c | 15 +++++++++++++++ gcc/config/i386/cpuid.h | 1 + gcc/config/i386/driver-i386.c | 6 +++++- gcc/config/i386/i386-c.c | 2 ++ gcc/config/i386/i386.c | 2 ++ gcc/config/i386/i386.h | 2 ++ gcc/config/i386/i386.opt | 4 ++++ gcc/doc/invoke.texi | 7 +++++-- 8 files changed, 36 insertions(+), 3 deletions(-) diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c index ada918e..8e2bcf6 100644 --- a/gcc/common/config/i386/i386-common.c +++ b/gcc/common/config/i386/i386-common.c @@ -140,6 +140,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI #define OPTION_MASK_ISA_IBT_SET OPTION_MASK_ISA_IBT #define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK +#define OPTION_MASK_ISA_VAES_SET OPTION_MASK_ISA_VAES /* Define a set of ISAs which aren't available when a given ISA is disabled. MMX and SSE ISAs are handled separately. */ @@ -208,6 +209,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI #define OPTION_MASK_ISA_IBT_UNSET OPTION_MASK_ISA_IBT #define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK +#define OPTION_MASK_ISA_VAES_UNSET OPTION_MASK_ISA_VAES /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same as -mno-sse4.1. */ @@ -532,6 +534,19 @@ ix86_handle_option (struct gcc_options *opts, } return true; + case OPT_mvaes: + if (value) + { + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_VAES_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_VAES_SET; + } + else + { + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_VAES_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_VAES_UNSET; + } + return true; + case OPT_mavx5124fmaps: if (value) { diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h index 8cb1848..51f6006 100644 --- a/gcc/config/i386/cpuid.h +++ b/gcc/config/i386/cpuid.h @@ -99,6 +99,7 @@ #define bit_OSPKE (1 << 4) #define bit_SHSTK (1 << 7) #define bit_GFNI (1 << 8) +#define bit_VAES (1 << 9) #define bit_AVX512VPOPCNTDQ (1 << 14) #define bit_RDPID (1 << 22) diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c index 8028399..3ef64e1 100644 --- a/gcc/config/i386/driver-i386.c +++ b/gcc/config/i386/driver-i386.c @@ -417,6 +417,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) unsigned int has_avx5124fmaps = 0, has_avx5124vnniw = 0; unsigned int has_gfni = 0; unsigned int has_ibt = 0, has_shstk = 0; + unsigned int has_vaes = 0; bool arch; @@ -507,6 +508,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) has_pku = ecx & bit_OSPKE; has_rdpid = ecx & bit_RDPID; has_gfni = ecx & bit_GFNI; + has_vaes = ecx & bit_VAES; has_avx5124vnniw = edx & bit_AVX5124VNNIW; has_avx5124fmaps = edx & bit_AVX5124FMAPS; @@ -1057,6 +1059,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) const char *gfni = has_gfni ? " -mgfni" : " -mno-gfni"; const char *ibt = has_ibt ? " -mibt" : " -mno-ibt"; const char *shstk = has_shstk ? " -mshstk" : " -mno-shstk"; + const char *vaes = has_vaes ? " -mvaes" : " -mno-vaes"; options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3, sse4a, cx16, sahf, movbe, aes, sha, pclmul, popcnt, abm, lwp, fma, fma4, xop, bmi, sgx, bmi2, @@ -1066,7 +1069,8 @@ const char *host_detect_local_cpu (int argc, const char **argv) avx512cd, avx512pf, prefetchwt1, clflushopt, xsavec, xsaves, avx512dq, avx512bw, avx512vl, avx512ifma, avx512vbmi, avx5124fmaps, avx5124vnniw, - clwb, mwaitx, clzero, pku, rdpid, gfni, ibt, shstk, NULL); + clwb, mwaitx, clzero, pku, rdpid, gfni, ibt, shstk, + vaes, NULL); } done: diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index 7f88bef..4919041 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -471,6 +471,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, if (flag_cf_protection != CF_NONE) def_or_undef (parse_in, "__CET__"); } + if (isa_flag2 & OPTION_MASK_ISA_VAES) + def_or_undef (parse_in, "__VAES__"); if (TARGET_IAMCU) { def_or_undef (parse_in, "__iamcu"); diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index ff0f6f8..d055724 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -2741,6 +2741,7 @@ ix86_target_string (HOST_WIDE_INT isa, HOST_WIDE_INT isa2, static struct ix86_target_opts isa2_opts[] = { { "-mgfni", OPTION_MASK_ISA_GFNI }, + { "-mvaes", OPTION_MASK_ISA_VAES }, { "-mrdpid", OPTION_MASK_ISA_RDPID }, { "-msgx", OPTION_MASK_ISA_SGX }, { "-mavx5124vnniw", OPTION_MASK_ISA_AVX5124VNNIW }, @@ -5303,6 +5304,7 @@ ix86_valid_target_attribute_inner_p (tree args, char *p_strings[], IX86_ATTR_ISA ("gfni", OPT_mgfni), IX86_ATTR_ISA ("ibt", OPT_mibt), IX86_ATTR_ISA ("shstk", OPT_mshstk), + IX86_ATTR_ISA ("vaes", OPT_mvaes), /* enum options */ IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_), diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 8fbad16..c662c06 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -105,6 +105,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_RDPID_P(x) TARGET_ISA_RDPID_P(x) #define TARGET_GFNI TARGET_ISA_GFNI #define TARGET_GFNI_P(x) TARGET_ISA_GFNI_P(x) +#define TARGET_VAES TARGET_ISA_VAES +#define TARGET_VAES_P(x) TARGET_ISA_VAES_P(x) #define TARGET_BMI TARGET_ISA_BMI #define TARGET_BMI_P(x) TARGET_ISA_BMI_P(x) #define TARGET_BMI2 TARGET_ISA_BMI2 diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 7c9dd47..c581c73 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -757,6 +757,10 @@ mgfni Target Report Mask(ISA_GFNI) Var(ix86_isa_flags2) Save Support GFNI built-in functions and code generation. +mvaes +Target Report Mask(ISA_VAES) Var(ix86_isa_flags2) Save +Support VAES built-in functions and code generation. + mbmi Target Report Mask(ISA_BMI) Var(ix86_isa_flags) Save Support BMI built-in functions and code generation. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index c312864..09e930f 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1204,7 +1204,7 @@ See RS/6000 and PowerPC Options. -msse4a -m3dnow -m3dnowa -mpopcnt -mabm -mbmi -mtbm -mfma4 -mxop @gol -mlzcnt -mbmi2 -mfxsr -mxsave -mxsaveopt -mrtm -mlwp -mmpx @gol -mmwaitx -mclzero -mpku -mthreads @gol --mcet -mibt -mshstk @gol +-mcet -mibt -mshstk -mvaes @gol -mms-bitfields -mno-align-stringops -minline-all-stringops @gol -minline-stringops-dynamically -mstringop-strategy=@var{alg} @gol -mmemcpy-strategy=@var{strategy} -mmemset-strategy=@var{strategy} @gol @@ -25864,11 +25864,14 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. @need 200 @itemx -mcet @opindex mcet +@need 200 +@itemx -mvaes +@opindex mvaes These switches enable the use of instructions in the MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, AVX, AVX2, AVX512F, AVX512PF, AVX512ER, AVX512CD, SHA, AES, PCLMUL, FSGSBASE, RDRND, F16C, FMA, SSE4A, FMA4, XOP, LWP, ABM, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA AVX512VBMI, BMI, BMI2, FXSR, -XSAVE, XSAVEOPT, LZCNT, RTM, MPX, MWAITX, PKU, IBT, SHSTK, +XSAVE, XSAVEOPT, LZCNT, RTM, MPX, MWAITX, PKU, IBT, SHSTK, VAES, 3DNow!@: or enhanced 3DNow!@: extended instruction sets. Each has a corresponding @option{-mno-} option to disable use of these instructions. -- 2.5.5