diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 36b1b2b..15dd176 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,20 @@
+2018-11-29  Wei Xiao  <wei3.xiao@intel.com>
+
+	* common/config/i386/i386-common.c (processor_names): Add cascadelake.
+	(processor_alias_table): Add cascadelake.
+	* config.gcc: Add -march=cascadelake.
+	* config/i386/driver-i386.c
+	(host_detect_local_cpu): Detect cascadelake.
+	* config/i386/i386-c.c (ix86_target_macros_internal): Handle cascadelake.
+	* config/i386/i386.c (ix86_cost): Add m_CASCADELAKE.
+	(processor_cost_table): Add cascadelake.
+	(get_builtin_code_for_version): Handle cascadelake.
+	(fold_builtin_cpu): Ditto.
+	* config/i386/i386.h (TARGET_CASCADELAKE, PROCESSOR_CASCADELAKE): New.
+	(PTA_CASCADELAKE): Ditto.
+	* doc/extend.texi: Add cascadelake.
+	* doc/invoke.texi: Add -march=cascadelake.
+
 2018-11-29  Alan Modra  <amodra@gmail.com>
 
 	* config/rs6000/rs6000.c (rs6000_emit_move): Disable long
@@ -2422,7 +2439,7 @@
 	* vr-values.c (vr_values::extract_range_from_comparison):
 	Clear equiv for constant singleton ranges.
 
-2018-11-12 Wei Xiao <wei3.xiao@intel.com>
+2018-11-12  Wei Xiao  <wei3.xiao@intel.com>
 
 	* config/i386/sse.md: Combine VFIXUPIMM* patterns
 	(<avx512>_fixupimm<mode>_maskz<round_saeonly_expand_name>): Update.
@@ -3673,7 +3690,7 @@
 	(pass_inc_dec::execute): Allocate and release
 	reg_next_debug_use.
 
-2018-11-06 Wei Xiao <wei3.xiao@intel.com>
+2018-11-06  Wei Xiao  <wei3.xiao@intel.com>
 
 	* config/i386/avx512fintrin.h: Update VFIXUPIMM* intrinsics.
 	(_mm512_fixupimm_round_pd): Update parameters and builtin.
diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
index 4238b43..f7a1fea 100644
--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@@ -1504,6 +1504,7 @@ const char *const processor_names[] =
   "cannonlake",
   "icelake-client",
   "icelake-server",
+  "cascadelake",
   "intel",
   "geode",
   "k6",
@@ -1584,6 +1585,8 @@ const pta processor_alias_table[] =
     PTA_ICELAKE_CLIENT},
   {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
     PTA_ICELAKE_SERVER},
+  {"cascadelake", PROCESSOR_CASCADELAKE, CPU_HASWELL,
+    PTA_CASCADELAKE},
   {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
   {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
   {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
diff --git a/gcc/config.gcc b/gcc/config.gcc
index f6162ed..31813c5 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -671,7 +671,7 @@ bdver3 bdver4 znver1 znver2 btver1 btver2 k8 k8-sse3 opteron \
 opteron-sse3 nocona core2 corei7 corei7-avx core-avx-i core-avx2 atom \
 slm nehalem westmere sandybridge ivybridge haswell broadwell bonnell \
 silvermont knl knm skylake-avx512 cannonlake icelake-client icelake-server \
-skylake goldmont goldmont-plus tremont x86-64 native"
+skylake goldmont goldmont-plus tremont cascadelake x86-64 native"
 
 # Additional x86 processors supported by --with-cpu=.  Each processor
 # MUST be separated by exactly one space.
diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c
index e910038..bcc16ef 100644
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -857,6 +857,9 @@ const char *host_detect_local_cpu (int argc, const char **argv)
 	      /* Assume Ice Lake.  */
 	      else if (has_gfni)
 		cpu = "icelake-client";
+	      /* Assume Cascade Lake.  */
+	      else if (has_avx512vnni)
+		cpu = "cascadelake";
 	      /* Assume Cannon Lake.  */
 	      else if (has_avx512vbmi)
 		cpu = "cannonlake";
diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c
index 16c6a2d..5c327dc 100644
--- a/gcc/config/i386/i386-c.c
+++ b/gcc/config/i386/i386-c.c
@@ -218,6 +218,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
       def_or_undef (parse_in, "__icelake_server");
       def_or_undef (parse_in, "__icelake_server__");
       break;
+    case PROCESSOR_CASCADELAKE:
+      def_or_undef (parse_in, "__cascadelake");
+      def_or_undef (parse_in, "__cascadelake__");
+      break;
     /* use PROCESSOR_max to not set/unset the arch macro.  */
     case PROCESSOR_max:
       break;
@@ -363,6 +367,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
     case PROCESSOR_LAKEMONT:
       def_or_undef (parse_in, "__tune_lakemont__");
       break;
+    case PROCESSOR_CASCADELAKE:
+      def_or_undef (parse_in, "__tune_cascadelake__");
+      break;
     case PROCESSOR_INTEL:
     case PROCESSOR_GENERIC:
       break;
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index cef809f..4226dd4 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -148,8 +148,9 @@ const struct processor_costs *ix86_cost = NULL;
 #define m_CANNONLAKE (HOST_WIDE_INT_1U<<PROCESSOR_CANNONLAKE)
 #define m_ICELAKE_CLIENT (HOST_WIDE_INT_1U<<PROCESSOR_ICELAKE_CLIENT)
 #define m_ICELAKE_SERVER (HOST_WIDE_INT_1U<<PROCESSOR_ICELAKE_SERVER)
+#define m_CASCADELAKE (HOST_WIDE_INT_1U<<PROCESSOR_CASCADELAKE)
 #define m_CORE_AVX512 (m_SKYLAKE_AVX512 | m_CANNONLAKE \
-		       | m_ICELAKE_CLIENT | m_ICELAKE_SERVER)
+		       | m_ICELAKE_CLIENT | m_ICELAKE_SERVER | m_CASCADELAKE)
 #define m_CORE_AVX2 (m_HASWELL | m_SKYLAKE | m_CORE_AVX512)
 #define m_CORE_ALL (m_CORE2 | m_NEHALEM  | m_SANDYBRIDGE | m_CORE_AVX2)
 #define m_GOLDMONT (HOST_WIDE_INT_1U<<PROCESSOR_GOLDMONT)
@@ -898,6 +899,7 @@ static const struct processor_costs *processor_cost_table[] =
   &skylake_cost,
   &skylake_cost,
   &skylake_cost,
+  &skylake_cost,
   &intel_cost,
   &geode_cost,
   &k6_cost,
@@ -31599,6 +31601,10 @@ get_builtin_code_for_version (tree decl, tree *predicate_list)
 	      arg_str = "icelake-server";
 	      priority = P_PROC_AVX512F;
 	      break;
+	    case PROCESSOR_CASCADELAKE:
+	      arg_str = "cascadelake";
+	      priority = P_PROC_AVX512F;
+	      break;
 	    case PROCESSOR_BONNELL:
 	      arg_str = "bonnell";
 	      priority = P_PROC_SSSE3;
@@ -32339,7 +32345,8 @@ fold_builtin_cpu (tree fndecl, tree *args)
     M_INTEL_COREI7_CANNONLAKE,
     M_INTEL_COREI7_ICELAKE_CLIENT,
     M_INTEL_COREI7_ICELAKE_SERVER,
-    M_AMDFAM17H_ZNVER2
+    M_AMDFAM17H_ZNVER2,
+    M_INTEL_COREI7_CASCADELAKE
   };
 
   static struct _arch_names_table
@@ -32366,6 +32373,7 @@ fold_builtin_cpu (tree fndecl, tree *args)
       {"cannonlake", M_INTEL_COREI7_CANNONLAKE},
       {"icelake-client", M_INTEL_COREI7_ICELAKE_CLIENT},
       {"icelake-server", M_INTEL_COREI7_ICELAKE_SERVER},
+      {"cascadelake", M_INTEL_COREI7_CASCADELAKE},
       {"bonnell", M_INTEL_BONNELL},
       {"silvermont", M_INTEL_SILVERMONT},
       {"goldmont", M_INTEL_GOLDMONT},
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index b9e726e..64fc5d4 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -407,6 +407,7 @@ extern const struct processor_costs ix86_size_cost;
 #define TARGET_CANNONLAKE (ix86_tune == PROCESSOR_CANNONLAKE)
 #define TARGET_ICELAKE_CLIENT (ix86_tune == PROCESSOR_ICELAKE_CLIENT)
 #define TARGET_ICELAKE_SERVER (ix86_tune == PROCESSOR_ICELAKE_SERVER)
+#define TARGET_CASCADELAKE (ix86_tune == PROCESSOR_CASCADELAKE)
 #define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL)
 #define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC)
 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
@@ -2261,6 +2262,7 @@ enum processor_type
   PROCESSOR_CANNONLAKE,
   PROCESSOR_ICELAKE_CLIENT,
   PROCESSOR_ICELAKE_SERVER,
+  PROCESSOR_CASCADELAKE,
   PROCESSOR_INTEL,
   PROCESSOR_GEODE,
   PROCESSOR_K6,
@@ -2377,6 +2379,7 @@ const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT
 const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
   | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
   | PTA_CLWB;
+const wide_int_bitmask PTA_CASCADELAKE = PTA_SKYLAKE_AVX512 | PTA_AVX512VNNI;
 const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
   | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
   | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 4e8be5b..a3f22e4 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -20540,6 +20540,9 @@ Intel Core i7 Ice Lake Client CPU.
 @item icelake-server
 Intel Core i7 Ice Lake Server CPU.
 
+@item cascadelake
+Intel Core i7 Cascadelake CPU.
+
 @item bonnell
 Intel Atom Bonnell CPU.
 
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index da642bc..340f35d 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -27763,6 +27763,12 @@ AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ,
 AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES, PCONFIG and WBNOINVD instruction
 set support.
 
+@item cascadelake
+Intel Cascadelake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
+SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
+BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
+AVX512VL, AVX512BW, AVX512DQ, AVX512CD and AVX512VNNI instruction set support.
+
 @item k6
 AMD K6 CPU with MMX instruction set support.
 
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 07b8e84..b840f98 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2018-11-29  Wei Xiao  <wei3.xiao@intel.com>
+
+	* g++.target/i386/mv16.C: Handle new march.
+	* gcc.target/i386/builtin_target.c: Ditto.
+	* gcc.target/i386/funcspec-56.inc: Ditto.
+
 2018-11-28  Martin Sebor  <msebor@redhat.com>
 
 	PR c/88065
@@ -1595,7 +1601,7 @@
 	* gcc.target/i386/pr18041-1.c: New testcase.
 	* gcc.target/i386/pr18041-2.c: Likewise.
 
-2018-11-06 Wei Xiao <wei3.xiao@intel.com>
+2018-11-06  Wei Xiao  <wei3.xiao@intel.com>
 
 	* gcc.target/i386/avx-1.c: Update tests for VFIXUPIMM* intrinsics.
 	* gcc.target/i386/avx512f-vfixupimmpd-1.c: Ditto.
diff --git a/gcc/testsuite/g++.target/i386/mv16.C b/gcc/testsuite/g++.target/i386/mv16.C
index 1091868..81e1511 100644
--- a/gcc/testsuite/g++.target/i386/mv16.C
+++ b/gcc/testsuite/g++.target/i386/mv16.C
@@ -68,6 +68,10 @@ int __attribute__ ((target("arch=icelake-server"))) foo () {
   return 18;
 }
 
+int __attribute__ ((target("arch=cascadelake"))) foo () {
+  return 19;
+}
+
 int main ()
 {
   int val = foo ();
@@ -94,6 +98,8 @@ int main ()
     assert (val == 17);
   else if (__builtin_cpu_is ("icelake-server"))
     assert (val == 18);
+  else if (__builtin_cpu_is ("cascadelake"))
+    assert (val == 19);
   else
     assert (val == 0);
 
diff --git a/gcc/testsuite/gcc.target/i386/builtin_target.c b/gcc/testsuite/gcc.target/i386/builtin_target.c
index 1a7a9f3..74c15d1 100644
--- a/gcc/testsuite/gcc.target/i386/builtin_target.c
+++ b/gcc/testsuite/gcc.target/i386/builtin_target.c
@@ -108,10 +108,22 @@ check_intel_cpu_model (unsigned int family, unsigned int model,
 	      assert (__builtin_cpu_is ("skylake"));
 	      break;
 	    case 0x55:
-	      /* Skylake with AVX-512 support.  */
-	      assert (__builtin_cpu_is ("corei7"));
-	      assert (__builtin_cpu_is ("skylake-avx512"));
-	      break;
+	      {
+	        unsigned int eax, ebx, ecx, edx;
+	        __cpuid_count (7, 0, eax, ebx, ecx, edx);
+	        assert (__builtin_cpu_is ("corei7"));
+	        if (ecx & bit_AVX512VNNI)
+	          {
+	            /* Cascadelake with AVX-512 support.  */
+	            assert (__builtin_cpu_is ("cascadelake"));
+	          }
+	        else
+	          {
+	             /* Skylake with AVX-512 support.  */
+	              assert (__builtin_cpu_is ("skylake-avx512"));
+	          }
+	        break;
+	      }
 	    case 0x66:
 	      /* Cannon Lake.  */
 	      assert (__builtin_cpu_is ("cannonlake"));
diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
index 437b12f..0eb83a7 100644
--- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
+++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
@@ -150,6 +150,7 @@ extern void test_arch_skylake_avx512 (void)	__attribute__((__target__("arch=skyl
 extern void test_arch_cannonlake (void)		__attribute__((__target__("arch=cannonlake")));
 extern void test_arch_icelake_client (void)	__attribute__((__target__("arch=icelake-client")));
 extern void test_arch_icelake_server (void)	__attribute__((__target__("arch=icelake-server")));
+extern void test_arch_cascadelake (void)	__attribute__((__target__("arch=cascadelake")));
 extern void test_arch_k8 (void)			__attribute__((__target__("arch=k8")));
 extern void test_arch_k8_sse3 (void)		__attribute__((__target__("arch=k8-sse3")));
 extern void test_arch_opteron (void)		__attribute__((__target__("arch=opteron")));
diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index a4bce25..8c36959 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,8 @@
+2018-11-28  Wei Xiao  <wei3.xiao@intel.com>
+
+	* config/i386/cpuinfo.c (get_intel_cpu): Handle cascadelake.
+	* config/i386/cpuinfo.h: Add INTEL_COREI7_CASCADELAKE.
+
 2018-11-27  Alan Modra  <amodra@gmail.com>
 
 	* config/rs6000/morestack.S (__stack_split_initialize),
diff --git a/libgcc/config/i386/cpuinfo.c b/libgcc/config/i386/cpuinfo.c
index 09f4d6f..2858452 100644
--- a/libgcc/config/i386/cpuinfo.c
+++ b/libgcc/config/i386/cpuinfo.c
@@ -215,9 +215,21 @@ get_intel_cpu (unsigned int family, unsigned int model, unsigned int brand_id)
 	      __cpu_model.__cpu_subtype = INTEL_COREI7_SKYLAKE;
 	      break;
 	    case 0x55:
-	      /* Skylake with AVX-512 support.  */
-	      __cpu_model.__cpu_type = INTEL_COREI7;
-	      __cpu_model.__cpu_subtype = INTEL_COREI7_SKYLAKE_AVX512;
+	      {
+		  unsigned int eax, ebx, ecx, edx;
+		  __cpu_model.__cpu_type = INTEL_COREI7;
+		  __cpuid_count (7, 0, eax, ebx, ecx, edx);
+		  if (ecx & bit_AVX512VNNI)
+		    {
+		      /* Cascadelake with AVX-512 support.  */
+		      __cpu_model.__cpu_subtype = INTEL_COREI7_CASCADELAKE;
+		    }
+		  else
+		    {
+		      /* Skylake with AVX-512 support.  */
+		      __cpu_model.__cpu_subtype = INTEL_COREI7_SKYLAKE_AVX512;
+		    }
+	      }
 	      break;
 	    case 0x66:
 	      /* Cannon Lake.  */
diff --git a/libgcc/config/i386/cpuinfo.h b/libgcc/config/i386/cpuinfo.h
index ac9c348..e731252 100644
--- a/libgcc/config/i386/cpuinfo.h
+++ b/libgcc/config/i386/cpuinfo.h
@@ -76,6 +76,7 @@ enum processor_subtypes
   INTEL_COREI7_ICELAKE_CLIENT,
   INTEL_COREI7_ICELAKE_SERVER,
   AMDFAM17H_ZNVER2,
+  INTEL_COREI7_CASCADELAKE,
   CPU_SUBTYPE_MAX
 };