diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index b19c700fc2fc46ce2f9af26777dbdcc46102befb..efa6f62dc9c99cd22b2ec77e6b9fca80768eff23 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1072,7 +1072,7 @@ (define_expand "sadv16qi" } ) -(define_insn "aarch64_aba" +(define_insn "aarch64_aba" [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w") (plus:VDQ_BHSI (minus:VDQ_BHSI (USMAX:VDQ_BHSI @@ -1577,7 +1577,7 @@ (define_expand "vec_set" ) -(define_insn "aarch64_mla" +(define_insn "aarch64_mla" [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w") (plus:VDQ_BHSI (mult:VDQ_BHSI (match_operand:VDQ_BHSI 2 "register_operand" "w") @@ -1588,7 +1588,7 @@ (define_insn "aarch64_mla" [(set_attr "type" "neon_mla_")] ) -(define_insn "*aarch64_mla_elt" +(define_insn "*aarch64_mla_elt" [(set (match_operand:VDQHS 0 "register_operand" "=w") (plus:VDQHS (mult:VDQHS @@ -1606,7 +1606,7 @@ (define_insn "*aarch64_mla_elt" [(set_attr "type" "neon_mla__scalar")] ) -(define_insn "*aarch64_mla_elt_" +(define_insn "*aarch64_mla_elt_" [(set (match_operand:VDQHS 0 "register_operand" "=w") (plus:VDQHS (mult:VDQHS @@ -1624,7 +1624,7 @@ (define_insn "*aarch64_mla_elt_" [(set_attr "type" "neon_mla__scalar")] ) -(define_insn "aarch64_mla_n" +(define_insn "aarch64_mla_n" [(set (match_operand:VDQHS 0 "register_operand" "=w") (plus:VDQHS (mult:VDQHS @@ -1637,7 +1637,7 @@ (define_insn "aarch64_mla_n" [(set_attr "type" "neon_mla__scalar")] ) -(define_insn "aarch64_mls" +(define_insn "aarch64_mls" [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w") (minus:VDQ_BHSI (match_operand:VDQ_BHSI 1 "register_operand" "0") (mult:VDQ_BHSI (match_operand:VDQ_BHSI 2 "register_operand" "w") @@ -1647,7 +1647,7 @@ (define_insn "aarch64_mls" [(set_attr "type" "neon_mla_")] ) -(define_insn "*aarch64_mls_elt" +(define_insn "*aarch64_mls_elt" [(set (match_operand:VDQHS 0 "register_operand" "=w") (minus:VDQHS (match_operand:VDQHS 4 "register_operand" "0") @@ -1665,7 +1665,7 @@ (define_insn "*aarch64_mls_elt" [(set_attr "type" "neon_mla__scalar")] ) -(define_insn "*aarch64_mls_elt_" +(define_insn "*aarch64_mls_elt_" [(set (match_operand:VDQHS 0 "register_operand" "=w") (minus:VDQHS (match_operand:VDQHS 4 "register_operand" "0") @@ -1683,7 +1683,7 @@ (define_insn "*aarch64_mls_elt_" [(set_attr "type" "neon_mla__scalar")] ) -(define_insn "aarch64_mls_n" +(define_insn "aarch64_mls_n" [(set (match_operand:VDQHS 0 "register_operand" "=w") (minus:VDQHS (match_operand:VDQHS 1 "register_operand" "0") @@ -3103,7 +3103,7 @@ (define_expand "aarch64_float_mls_laneq" } ) -(define_insn "fma4" +(define_insn "fma4" [(set (match_operand:VHSDF 0 "register_operand" "=w") (fma:VHSDF (match_operand:VHSDF 1 "register_operand" "w") (match_operand:VHSDF 2 "register_operand" "w") @@ -3113,7 +3113,7 @@ (define_insn "fma4" [(set_attr "type" "neon_fp_mla_")] ) -(define_insn "*aarch64_fma4_elt" +(define_insn "*aarch64_fma4_elt" [(set (match_operand:VDQF 0 "register_operand" "=w") (fma:VDQF (vec_duplicate:VDQF @@ -3130,7 +3130,7 @@ (define_insn "*aarch64_fma4_elt" [(set_attr "type" "neon_fp_mla__scalar")] ) -(define_insn "*aarch64_fma4_elt_" +(define_insn "*aarch64_fma4_elt_" [(set (match_operand:VDQSF 0 "register_operand" "=w") (fma:VDQSF (vec_duplicate:VDQSF @@ -3147,7 +3147,7 @@ (define_insn "*aarch64_fma4_elt_" [(set_attr "type" "neon_fp_mla__scalar")] ) -(define_insn "*aarch64_fma4_elt_from_dup" +(define_insn "*aarch64_fma4_elt_from_dup" [(set (match_operand:VMUL 0 "register_operand" "=w") (fma:VMUL (vec_duplicate:VMUL @@ -3175,7 +3175,7 @@ (define_insn "*aarch64_fma4_elt_to_64v2df" [(set_attr "type" "neon_fp_mla_d_scalar_q")] ) -(define_insn "fnma4" +(define_insn "fnma4" [(set (match_operand:VHSDF 0 "register_operand" "=w") (fma:VHSDF (neg:VHSDF (match_operand:VHSDF 1 "register_operand" "w")) @@ -3186,7 +3186,7 @@ (define_insn "fnma4" [(set_attr "type" "neon_fp_mla_")] ) -(define_insn "*aarch64_fnma4_elt" +(define_insn "*aarch64_fnma4_elt" [(set (match_operand:VDQF 0 "register_operand" "=w") (fma:VDQF (neg:VDQF @@ -3204,7 +3204,7 @@ (define_insn "*aarch64_fnma4_elt" [(set_attr "type" "neon_fp_mla__scalar")] ) -(define_insn "*aarch64_fnma4_elt_" +(define_insn "*aarch64_fnma4_elt_" [(set (match_operand:VDQSF 0 "register_operand" "=w") (fma:VDQSF (neg:VDQSF @@ -3222,7 +3222,7 @@ (define_insn "*aarch64_fnma4_elt_" [(set_attr "type" "neon_fp_mla__scalar")] ) -(define_insn "*aarch64_fnma4_elt_from_dup" +(define_insn "*aarch64_fnma4_elt_from_dup" [(set (match_operand:VMUL 0 "register_operand" "=w") (fma:VMUL (neg:VMUL @@ -3834,7 +3834,7 @@ (define_insn "aarch64_reduc__internal" ;; Some forms of straight-line code may generate the equivalent form ;; in *aarch64_simd_bsl_alt. -(define_insn "aarch64_simd_bsl_internal" +(define_insn "aarch64_simd_bsl_internal" [(set (match_operand:VDQ_I 0 "register_operand" "=w,w,w") (xor:VDQ_I (and:VDQ_I @@ -3858,7 +3858,7 @@ (define_insn "aarch64_simd_bsl_internal" ;; the first. The two are equivalent but since recog doesn't try all ;; permutations of commutative operations, we have to have a separate pattern. -(define_insn "*aarch64_simd_bsl_alt" +(define_insn "*aarch64_simd_bsl_alt" [(set (match_operand:VDQ_I 0 "register_operand" "=w,w,w") (xor:VDQ_I (and:VDQ_I diff --git a/gcc/testsuite/gcc.target/aarch64/simd/pr99195_3.c b/gcc/testsuite/gcc.target/aarch64/simd/pr99195_3.c new file mode 100644 index 0000000000000000000000000000000000000000..c751924e8d1b3186b8955b9944d7ece9dd4d6edd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/pr99195_3.c @@ -0,0 +1,68 @@ +/* PR target/99195. */ +/* Check that we take advantage of 64-bit Advanced SIMD operations clearing + the top half of the vector register and no explicit zeroing instructions + are emitted. */ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +#include + +#define TERNARY(OT,IT,OP,S) \ +OT \ +foo_##OP##_##S (IT a, IT b, IT c) \ +{ \ + IT zeros = vcreate_##S (0); \ + return vcombine_##S (v##OP##_##S (a, b, c), zeros); \ +} + +#define FUNC(T,IS,OS,OP,S) TERNARY (T##x##OS##_t, T##x##IS##_t, OP, S) + +#define OPTWO(T,IS,OS,S,OP1,OP2) \ +FUNC (T, IS, OS, OP1, S) \ +FUNC (T, IS, OS, OP2, S) + +#define OPTHREE(T, IS, OS, S, OP1, OP2, OP3) \ +FUNC (T, IS, OS, OP1, S) \ +OPTWO (T, IS, OS, S, OP2, OP3) + +#define OPFOUR(T,IS,OS,S,OP1,OP2,OP3,OP4) \ +FUNC (T, IS, OS, OP1, S) \ +OPTHREE (T, IS, OS, S, OP2, OP3, OP4) + +OPTHREE (int8, 8, 16, s8, mla, mls, aba) +OPTHREE (int16, 4, 8, s16, mla, mls, aba) +OPTHREE (int32, 2, 4, s32, mla, mls, aba) + +OPFOUR (uint8, 8, 16, u8, mla, mls, aba, bsl) +OPFOUR (uint16, 4, 8, u16, mla, mls, aba, bsl) +OPFOUR (uint32, 2, 4, u32, mla, mls, aba, bsl) + +OPTHREE (float32, 2, 4, f32, mla, fma, fms) + +#undef FUNC +#define TERNARY_LANE(OT,IT,OP,S) \ +OT \ +foo_##OP##_##S (IT a, IT b, IT c) \ +{ \ + IT zeros = vcreate_##S (0); \ + return vcombine_##S (v##OP##_##S (a, b, c, 0), zeros); \ +} \ +OT \ +foo_##OP##_##S##_lane1 (IT a, IT b, IT c) \ +{ \ + IT zeros = vcreate_##S (0); \ + return vcombine_##S (v##OP##_##S (a, b, c, 1), zeros); \ +} + +#define FUNC(T,IS,OS,OP,S) TERNARY_LANE (T##x##OS##_t, T##x##IS##_t, OP, S) +OPTWO (int16, 4, 8, s16, mla_lane, mls_lane) +OPTWO (int32, 2, 4, s32, mla_lane, mls_lane) + +OPTWO (uint16, 4, 8, u16, mla_lane, mls_lane) +OPTWO (uint32, 2, 4, u32, mla_lane, mls_lane) + +OPTHREE (float32, 2, 4, f32, mla_lane, fma_lane, fms_lane) + +/* { dg-final { scan-assembler-not {\tfmov\t} } } */ +/* { dg-final { scan-assembler-not {\tmov\t} } } */ +