From: Pan Li <pan2...@intel.com>
The avg3_floor pattern leverage the add and shift rtl
with the DOUBLE_TRUNC mode iterator. Aka, RVVDImode
iterator will generate avg3rvvsimode_floor, only the
element size QI, HI and SI are allowed.
Thus, this patch would like to support the DImode by
the standard name, with the iterator V_VLSI_D.
The below test suites are passed for this patch series.
* The rv64gcv fully regression test.
gcc/ChangeLog:
* config/riscv/autovec.md (avg<mode>3_floor): Add new
pattern of avg3_floor for rvv DImode.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/avg.h: Add int128 type when
xlen == 64.
* gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i32.c:
Suppress __int128 warning for run test.
* gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i32-from-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/avg_floor-run-1-i16-from-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/avg_floor-run-1-i16-from-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/avg_floor-run-1-i32-from-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c: New test.
* gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i128.c: New test.
Signed-off-by: Pan Li <pan2...@intel.com>
---
gcc/config/riscv/autovec.md | 13 +++++++++++++
gcc/testsuite/gcc.target/riscv/rvv/autovec/avg.h | 5 +++++
.../rvv/autovec/avg_ceil-run-1-i16-from-i32.c | 2 +-
.../rvv/autovec/avg_ceil-run-1-i16-from-i64.c | 2 +-
.../rvv/autovec/avg_ceil-run-1-i32-from-i64.c | 2 +-
.../rvv/autovec/avg_ceil-run-1-i8-from-i16.c | 2 +-
.../rvv/autovec/avg_ceil-run-1-i8-from-i32.c | 2 +-
.../rvv/autovec/avg_ceil-run-1-i8-from-i64.c | 2 +-
.../rvv/autovec/avg_floor-1-i64-from-i128.c | 12 ++++++++++++
.../rvv/autovec/avg_floor-run-1-i16-from-i32.c | 2 +-
.../rvv/autovec/avg_floor-run-1-i16-from-i64.c | 2 +-
.../rvv/autovec/avg_floor-run-1-i32-from-i64.c | 2 +-
.../rvv/autovec/avg_floor-run-1-i8-from-i128.c | 16 ++++++++++++++++
.../rvv/autovec/avg_floor-run-1-i8-from-i16.c | 2 +-
.../rvv/autovec/avg_floor-run-1-i8-from-i32.c | 2 +-
.../rvv/autovec/avg_floor-run-1-i8-from-i64.c | 2 +-
16 files changed, 58 insertions(+), 12 deletions(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i128.c
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 94a61bdc5cf..2e86826f286 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2499,6 +2499,19 @@ (define_expand "avg<v_double_trunc>3_floor"
}
)
+(define_expand "avg<mode>3_floor"
+ [(match_operand:V_VLSI_D 0 "register_operand")
+ (match_operand:V_VLSI_D 1 "register_operand")
+ (match_operand:V_VLSI_D 2 "register_operand")]
+ "TARGET_VECTOR"
+ {
+ insn_code icode = code_for_pred (UNSPEC_VAADD, <MODE>mode);
+ riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP_VXRM_RDN,
+ operands);
+ DONE;
+ }
+)
+
(define_expand "avg<v_double_trunc>3_ceil"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand")
(truncate:<V_DOUBLE_TRUNC>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg.h
index 4aeb637bba7..2de7d7c49df 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg.h
@@ -3,6 +3,11 @@
#include <stdint.h>
+#if __riscv_xlen == 64
+typedef unsigned __int128 uint128_t;
+typedef signed __int128 int128_t;
+#endif
+
#define DEF_AVG_0(NT, WT, NAME) \
__attribute__((noinline)) \
void \
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i32.c
index 1fa080b3933..3d872a8a4b5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i32.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -O3" } */
+/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */
#include "avg.h"
#include "avg_data.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i64.c
index deec763131a..eda9736e42d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i64.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -O3" } */
+/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */
#include "avg.h"
#include "avg_data.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i32-from-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i32-from-i64.c
index fa720006492..21cbb9478bc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i32-from-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i32-from-i64.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -O3" } */
+/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */
#include "avg.h"
#include "avg_data.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i16.c
index 6865cf26762..fd91b6fc48e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i16.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -O3" } */
+/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */
#include "avg.h"
#include "avg_data.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i32.c
index 78620f4c920..38f49206611 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i32.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -O3" } */
+/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */
#include "avg.h"
#include "avg_data.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i64.c
index b2c763cad61..f65ee15a09b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i64.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -O3" } */
+/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */
#include "avg.h"
#include "avg_data.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c
new file mode 100644
index 00000000000..c94dfc2bde2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "avg.h"
+
+#define NT int64_t
+#define WT int128_t
+
+DEF_AVG_0(NT, WT, avg_floor)
+
+/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */
+/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i16-from-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i16-from-i32.c
index 9d0dd618e56..92239a28160 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i16-from-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i16-from-i32.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -O3" } */
+/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */
#include "avg.h"
#include "avg_data.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i16-from-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i16-from-i64.c
index 2736baa36e8..5716c2967d9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i16-from-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i16-from-i64.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -O3" } */
+/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */
#include "avg.h"
#include "avg_data.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i32-from-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i32-from-i64.c
index 2334045bfa4..705e09126bc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i32-from-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i32-from-i64.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -O3" } */
+/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */
#include "avg.h"
#include "avg_data.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i128.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i128.c
new file mode 100644
index 00000000000..784e20875e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i128.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v && rv64 } } } */
+/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */
+
+#include "avg.h"
+#include "avg_data.h"
+
+#define WT int128_t
+#define NT int8_t
+#define NAME avg_floor
+
+DEF_AVG_0_WRAP(NT, WT, NAME)
+
+#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME)
+#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_0_WRAP(NT, WT, NAME, a,
b, out, n)
+
+#include "avg_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i16.c
index 836474844d2..abe5c5b81e9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i16.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -O3" } */
+/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */
#include "avg.h"
#include "avg_data.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i32.c
index 157c9360ce0..355b90fabfc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i32.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -O3" } */
+/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */
#include "avg.h"
#include "avg_data.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i64.c
index 2db0d3cb37e..a9ae96fdcb8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i64.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -O3" } */
+/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */
#include "avg.h"
#include "avg_data.h"
--
2.43.0
