Hi Claudiu, > -----Original Message----- > From: [email protected] <claudiu.zissulescu- > [email protected]> > Sent: 05 November 2025 09:09 > To: [email protected] > Cc: [email protected]; [email protected]; Tamar Christina > <[email protected]>; Wilco Dijkstra <[email protected]> > Subject: [PATCH v6 2/6] target-insns.def: (compose_tag) New pattern. > > From: Claudiu Zissulescu <[email protected]> > > Add a new target instruction used by hardware-assisted sanitizers on > architectures providing memory-tagging instructions. This instruction > is used to compute assign tags at a fixed offset from a tagged address > base. For example, in AArch64 case, this pattern instantiate `addg` > instruction.
Patch is OK. Sorry for the long delay. Thanks, Tamar > > gcc/doc/ > > * md.texi (compose_tag): Add documentation. > > gcc/ > > * target-insns.def (compose_tag): New target instruction. > > Signed-off-by: Claudiu Zissulescu <[email protected]> > --- > gcc/doc/md.texi | 5 +++++ > gcc/target-insns.def | 1 + > 2 files changed, 6 insertions(+) > > diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi > index 82fef3ef867..acd53da560e 100644 > --- a/gcc/doc/md.texi > +++ b/gcc/doc/md.texi > @@ -8608,6 +8608,11 @@ This pattern tags an object that begins at the > address specified by > operand 0, has the byte size indicated by the operand 2, and uses the > tag from operand 1. > > +@cindex @code{compose_tag} instruction pattern > +This pattern composes a tagged address specified by operand 1 with > +mode @code{ptr_mode}, with an integer operand 2 representing the tag > +offset. It returns the result in operand 0 with mode @code{ptr_mode}. > + > @cindex @code{clear_cache} instruction pattern > @item @samp{clear_cache} > This pattern, if defined, flushes the instruction cache for a region of > diff --git a/gcc/target-insns.def b/gcc/target-insns.def > index 16e1d8cf565..bfdc078378f 100644 > --- a/gcc/target-insns.def > +++ b/gcc/target-insns.def > @@ -47,6 +47,7 @@ DEF_TARGET_INSN (call_value_pop, (rtx x0, rtx x1, rtx > opt2, rtx opt3, > DEF_TARGET_INSN (casesi, (rtx x0, rtx x1, rtx x2, rtx x3, rtx x4)) > DEF_TARGET_INSN (check_stack, (rtx x0)) > DEF_TARGET_INSN (clear_cache, (rtx x0, rtx x1)) > +DEF_TARGET_INSN (compose_tag, (rtx x0, rtx x1, rtx x2)) > DEF_TARGET_INSN (doloop_begin, (rtx x0, rtx x1)) > DEF_TARGET_INSN (doloop_end, (rtx x0, rtx x1)) > DEF_TARGET_INSN (eh_return, (rtx x0)) > -- > 2.51.0
