Combine was prevented for some time from combining two ashifts when
the substituted insn couldn't be removed, and r15-7801 changed the
expectations to match.
Combine was later allowed to combine such insns, and the scheduler
reorders the insns so that the expected function body doesn't match.
I've added options to disable scheduling, and I've restored the
combine expectation.
Regstrapped on x86_64-linux-gnu along with other patches in this batch;
also tested with targets riscv64-elf and riscv32-elf on the same host,
both trunk and gcc-15. Ok to install?
for gcc/testsuite/ChangeLog
* gcc.target/riscv/rvv/autovec/bug-3.c: Disable scheduling,
and restore expectation of slli combine.
---
gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c
index 2d5f4c2e0de0f..6075d689cc4c3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -mrvv-max-lmul=m8
-mrvv-vector-bits=scalable -fno-vect-cost-model -O2 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -mrvv-max-lmul=m8
-mrvv-vector-bits=scalable -fno-vect-cost-model -O2 -ffast-math
-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#define N 16
@@ -31,8 +31,7 @@ _Complex float res[N] =
** ...
** csrr\s+[atx][0-9]+,\s*vlenb
** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*1
-** ...
-** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32
+** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*33
** ...
*/
void
--
Alexandre Oliva, happy hacker https://blog.lx.oliva.nom.br/
Free Software Activist FSFLA co-founder GNU Toolchain Engineer
More tolerance and less prejudice are key for inclusion and diversity.
Excluding neuro-others for not behaving ""normal"" is *not* inclusive!
