diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index b5f53d2..7710f1f 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -196,6 +196,8 @@ bool aarch64_modes_tieable_p (enum machine_mode mode1, bool aarch64_move_imm (HOST_WIDE_INT, enum machine_mode); bool aarch64_mov_operand_p (rtx, enum aarch64_symbol_context, enum machine_mode); +int aarch64_simd_attr_length_rglist (enum machine_mode); +rtx aarch64_reverse_mask (enum machine_mode); bool aarch64_offset_7bit_signed_scaled_p (enum machine_mode, HOST_WIDE_INT); char *aarch64_output_scalar_simd_mov_immediate (rtx, enum machine_mode); char *aarch64_output_simd_mov_immediate (rtx, enum machine_mode, unsigned); diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index cab26a3..126653f 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3981,7 +3981,7 @@ ;; Patterns for vector struct loads and stores. -(define_insn "vec_load_lanesoi" +(define_insn "aarch64_simd_ld2" [(set (match_operand:OI 0 "register_operand" "=w") (unspec:OI [(match_operand:OI 1 "aarch64_simd_struct_operand" "Utv") (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] @@ -3991,7 +3991,26 @@ [(set_attr "type" "neon_load2_2reg")] ) -(define_insn "vec_store_lanesoi" +(define_expand "vec_load_lanesoi" + [(set (match_operand:OI 0 "register_operand" "=w") + (unspec:OI [(match_operand:OI 1 "aarch64_simd_struct_operand" "Utv") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_LD2))] + "TARGET_SIMD" +{ + if (BYTES_BIG_ENDIAN) + { + rtx tmp = gen_reg_rtx (OImode); + rtx mask = aarch64_reverse_mask (mode); + emit_insn (gen_aarch64_simd_ld2 (tmp, operands[1])); + emit_insn (gen_aarch64_rev_reglistoi (operands[0], tmp, mask)); + } + else + emit_insn (gen_aarch64_simd_ld2 (operands[0], operands[1])); + DONE; +}) + +(define_insn "aarch64_simd_st2" [(set (match_operand:OI 0 "aarch64_simd_struct_operand" "=Utv") (unspec:OI [(match_operand:OI 1 "register_operand" "w") (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] @@ -4012,7 +4031,26 @@ [(set_attr "type" "neon_store3_one_lane")] ) -(define_insn "vec_load_lanesci" +(define_expand "vec_store_lanesoi" + [(set (match_operand:OI 0 "aarch64_simd_struct_operand" "=Utv") + (unspec:OI [(match_operand:OI 1 "register_operand" "w") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_ST2))] + "TARGET_SIMD" +{ + if (BYTES_BIG_ENDIAN) + { + rtx tmp = gen_reg_rtx (OImode); + rtx mask = aarch64_reverse_mask (mode); + emit_insn (gen_aarch64_rev_reglistoi (tmp, operands[1], mask)); + emit_insn (gen_aarch64_simd_st2 (operands[0], tmp)); + } + else + emit_insn (gen_aarch64_simd_st2 (operands[0], operands[1])); + DONE; +}) + +(define_insn "aarch64_simd_ld3" [(set (match_operand:CI 0 "register_operand" "=w") (unspec:CI [(match_operand:CI 1 "aarch64_simd_struct_operand" "Utv") (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] @@ -4022,7 +4060,26 @@ [(set_attr "type" "neon_load3_3reg")] ) -(define_insn "vec_store_lanesci" +(define_expand "vec_load_lanesci" + [(set (match_operand:CI 0 "register_operand" "=w") + (unspec:CI [(match_operand:CI 1 "aarch64_simd_struct_operand" "Utv") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_LD3))] + "TARGET_SIMD" +{ + if (BYTES_BIG_ENDIAN) + { + rtx tmp = gen_reg_rtx (CImode); + rtx mask = aarch64_reverse_mask (mode); + emit_insn (gen_aarch64_simd_ld3 (tmp, operands[1])); + emit_insn (gen_aarch64_rev_reglistci (operands[0], tmp, mask)); + } + else + emit_insn (gen_aarch64_simd_ld3 (operands[0], operands[1])); + DONE; +}) + +(define_insn "aarch64_simd_st3" [(set (match_operand:CI 0 "aarch64_simd_struct_operand" "=Utv") (unspec:CI [(match_operand:CI 1 "register_operand" "w") (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] @@ -4043,7 +4100,26 @@ [(set_attr "type" "neon_store3_one_lane")] ) -(define_insn "vec_load_lanesxi" +(define_expand "vec_store_lanesci" + [(set (match_operand:CI 0 "aarch64_simd_struct_operand" "=Utv") + (unspec:CI [(match_operand:CI 1 "register_operand" "w") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_ST3))] + "TARGET_SIMD" +{ + if (BYTES_BIG_ENDIAN) + { + rtx tmp = gen_reg_rtx (CImode); + rtx mask = aarch64_reverse_mask (mode); + emit_insn (gen_aarch64_rev_reglistci (tmp, operands[1], mask)); + emit_insn (gen_aarch64_simd_st3 (operands[0], tmp)); + } + else + emit_insn (gen_aarch64_simd_st3 (operands[0], operands[1])); + DONE; +}) + +(define_insn "aarch64_simd_ld4" [(set (match_operand:XI 0 "register_operand" "=w") (unspec:XI [(match_operand:XI 1 "aarch64_simd_struct_operand" "Utv") (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] @@ -4053,7 +4129,26 @@ [(set_attr "type" "neon_load4_4reg")] ) -(define_insn "vec_store_lanesxi" +(define_expand "vec_load_lanesxi" + [(set (match_operand:XI 0 "register_operand" "=w") + (unspec:XI [(match_operand:XI 1 "aarch64_simd_struct_operand" "Utv") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_LD4))] + "TARGET_SIMD" +{ + if (BYTES_BIG_ENDIAN) + { + rtx tmp = gen_reg_rtx (XImode); + rtx mask = aarch64_reverse_mask (mode); + emit_insn (gen_aarch64_simd_ld4 (tmp, operands[1])); + emit_insn (gen_aarch64_rev_reglistxi (operands[0], tmp, mask)); + } + else + emit_insn (gen_aarch64_simd_ld4 (operands[0], operands[1])); + DONE; +}) + +(define_insn "aarch64_simd_st4" [(set (match_operand:XI 0 "aarch64_simd_struct_operand" "=Utv") (unspec:XI [(match_operand:XI 1 "register_operand" "w") (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] @@ -4074,6 +4169,50 @@ [(set_attr "type" "neon_store4_one_lane")] ) +(define_expand "vec_store_lanesxi" + [(set (match_operand:XI 0 "aarch64_simd_struct_operand" "=Utv") + (unspec:XI [(match_operand:XI 1 "register_operand" "w") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_ST4))] + "TARGET_SIMD" +{ + if (BYTES_BIG_ENDIAN) + { + rtx tmp = gen_reg_rtx (XImode); + rtx mask = aarch64_reverse_mask (mode); + emit_insn (gen_aarch64_rev_reglistxi (tmp, operands[1], mask)); + emit_insn (gen_aarch64_simd_st4 (operands[0], tmp)); + } + else + emit_insn (gen_aarch64_simd_st4 (operands[0], operands[1])); + DONE; +}) + +(define_insn_and_split "aarch64_rev_reglist" +[(set (match_operand:VSTRUCT 0 "register_operand" "=&w") + (unspec:VSTRUCT + [(match_operand:VSTRUCT 1 "register_operand" "w") + (match_operand:V16QI 2 "register_operand" "w")] + UNSPEC_REV_REGLIST))] + "TARGET_SIMD" + "#" + "&& reload_completed" + [(const_int 0)] +{ + int i; + int nregs = GET_MODE_SIZE (mode) / UNITS_PER_VREG; + for (i = 0; i < nregs; i++) + { + rtx op0 = gen_rtx_REG (V16QImode, REGNO (operands[0]) + i); + rtx op1 = gen_rtx_REG (V16QImode, REGNO (operands[1]) + i); + emit_insn (gen_aarch64_tbl1v16qi (op0, op1, operands[2])); + } + DONE; +} + [(set_attr "type" "neon_tbl1_q") + (set_attr "length" "")] +) + ;; Reload patterns for AdvSIMD register list operands. (define_expand "mov" diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 5144c35..9d05058 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -8072,6 +8072,14 @@ aarch64_simd_attr_length_move (rtx_insn *insn) return 4; } +/* Compute and return the length of aarch64_simd_reglist, where is + one of VSTRUCT modes: OI, CI, EI, or XI. */ +int +aarch64_simd_attr_length_rglist (enum machine_mode mode) +{ + return (GET_MODE_SIZE (mode) / UNITS_PER_VREG) * 4; +} + /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum alignment of a vector to 128 bits. */ static HOST_WIDE_INT @@ -9600,6 +9608,27 @@ aarch64_cannot_change_mode_class (enum machine_mode from, return true; } +rtx +aarch64_reverse_mask (enum machine_mode mode) +{ + /* We have to reverse each vector because we dont have + a permuted load that can reverse-load according to ABI rules. */ + rtx mask; + rtvec v = rtvec_alloc (16); + int i, j; + int nunits = GET_MODE_NUNITS (mode); + int usize = GET_MODE_UNIT_SIZE (mode); + + gcc_assert (BYTES_BIG_ENDIAN); + gcc_assert (AARCH64_VALID_SIMD_QREG_MODE (mode)); + + for (i = 0; i < nunits; i++) + for (j = 0; j < usize; j++) + RTVEC_ELT (v, (i * usize + j)) = GEN_INT (((i+1) * usize) - 1 - j); + mask = gen_rtx_CONST_VECTOR (V16QImode, v); + return force_reg (V16QImode, mask); +} + /* Implement MODES_TIEABLE_P. */ bool diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index efd006f..05e842c 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -299,6 +299,7 @@ UNSPEC_SHA256SU1 ; Used in aarch64-simd.md. UNSPEC_PMULL ; Used in aarch64-simd.md. UNSPEC_PMULL2 ; Used in aarch64-simd.md. + UNSPEC_REV_REGLIST ; Used in aarch64-simd.md. ]) ;; ------------------------------------------------------------------- @@ -668,6 +669,8 @@ (V2DI "p") (V2DF "p") (V2SF "p") (V4SF "v")]) +(define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")]) + ;; ------------------------------------------------------------------- ;; Code Iterators ;; -------------------------------------------------------------------