diff -Naur gcc-4.2-20060218orig/gcc/config/xc16x/lib1funcs.asm gcc-4.2-20060218/gcc/config/xc16x/lib1funcs.asm
--- gcc-4.2-20060218orig/gcc/config/xc16x/lib1funcs.asm	1970-01-01 05:30:00.000000000 +0530
+++ gcc-4.2-20060218/gcc/config/xc16x/lib1funcs.asm	2006-03-03 17:11:45.736499488 +0530
@@ -0,0 +1,422 @@
+;; GCC Library functions for Infineon xc16x
+;; Copyright (C)  2006 Free Software Foundation, Inc.
+
+;; Contributed by Shrirang Khisti on behalf of KPIT Cummins Infosystems Ltd.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+;Function For unsigned division in SI mode (32 bits)
+
+.section .text
+.align 2
+.global ___udivsi3
+___udivsi3:
+
+;Temporary 
+
+	mov [-r0],r2
+	prior r2,r11
+	jmpr cc_NZ,.l1
+	mov MDL,r9
+	divu r10
+	mov r2,MDH
+	mov r9,MDL
+	mov MDH,r2
+	mov MDL,r8
+	divlu r10  
+	mov r8,MDL
+	mov r4,r8
+	mov r5,r9
+	mov r2,[r0+]
+
+	#ifdef __xc16xL__   
+	   rets
+	#else 
+	   ret
+	#endif   
+
+
+.l1:
+
+	mov [-r0],r9
+	mov [-r0],r8
+	mov [-r0],r10
+	mov [-r0],r11
+
+	cmp r2,#0
+	jmpr cc_NZ ,.l2
+	mov r8,r9
+	mov r9,#0x0
+	jmpr cc_UC,.l3
+
+.l2:
+	shl r11,r2
+	neg r2
+	shr r10,r2
+	or r11,r10
+	mov r10,r9
+	shr r9,r2
+	shr r8,r2
+	neg r2
+	shl r10,r2
+	or r8,r10
+
+.l3:
+	mov MDH,r9
+	mov MDL,r8
+	divlu r11
+	mov r8,MDL
+	mov r11,[r0+]
+	mov r10,[r0+]
+	mulu r8,r11
+	mov r9,MDL
+	mulu r8,r10
+	add r9,MDH
+	mov r11,MDL
+	jmpr cc_NC,.l4
+	add r0,#0x4
+	jmpr cc_UC,.l5
+
+.l4:
+	sub r11,[r0+]
+	subc r9,[r0+]
+	jmpr cc_ULE,.l6
+
+.l5: 
+	sub r8,#0x1
+.l6: 
+	mov r9,#0x0
+        mov r5,r9
+        mov r4,r8
+        mov r2,[r0+]
+
+	#ifdef __xc16xL__   
+	   rets
+	#else 
+	   ret
+	#endif   
+
+     
+;Function For signed division in SI mode (32 bits)
+
+.align 2
+.global ___divsi3
+
+___divsi3:
+
+
+
+	mov [-r0],r1
+	mov r1,r9
+	jmpr cc_NN,.dl1
+	neg r9
+	neg r8
+	subc r9,#0x0
+
+.dl1:
+	jnb r11.15,.dl2
+	cpl r1
+	neg r11
+	neg r10
+	subc r11,#0x0
+
+.dl2: 
+	#ifdef __xc16xL__
+	calls #SEG:___udivsi3,#SOF:___udivsi3
+	#else
+;calla cc_UC,___umodsi3
+	calla cc_UC,___udivsi3
+	#endif
+	jnb r1.15,.dl3
+	neg r5
+	neg r4
+	subc r5,#0x0
+
+.dl3:
+	mov r1,[r0+]
+
+	#ifdef __xc16xL__   
+	   rets
+	#else 
+	   ret
+	#endif   
+
+    
+ ;Function For calculating signed mod in SI mode (32 bits)   
+
+
+.align 2
+.global ___modsi3
+___modsi3:
+	mov [-r0],r1
+	mov r1,r9
+	jmpr cc_NN,.ml1
+	neg r9
+	neg r8
+	subc r9,#0x0
+
+.ml1:
+	jnb r11.15,.ml2
+	neg r11
+	neg r10
+	subc r11,#0x0
+
+.ml2:
+	#ifdef __xc16xL__
+	calls #SEG:___umodsi3,#SOF:___umodsi3
+	#else
+	calla cc_UC,___umodsi3
+	#endif
+	jnb r1.15,.ml3
+	neg r5
+	neg r4
+	subc r5,#0x0
+
+.ml3: 
+	mov r1,[r0+]
+	#ifdef __xc16xL__   
+	   rets
+	#else 
+	   ret
+	#endif   
+
+
+
+
+;Function For calculating unsigned mod in SI mode (32 bits)   
+
+.align 2
+.global ___umodsi3
+
+___umodsi3:
+
+mov [-r0],r2
+prior r2,r11
+jmpr cc_NZ,.uml1
+mov MDL,r9
+divu r10
+mov MDL,r8
+divlu r10
+mov r8,MDH
+mov r9,MDL
+mov r9,#0x0
+mov r5,r9
+mov r4,r8
+mov r2,[r0+]
+
+#ifdef __xc16xL__   
+   rets
+#else 
+   ret
+#endif   
+
+.uml1: mov [-r0],r9
+    mov [-r0],r8
+    mov [-r0],r10
+    mov [-r0],r11
+    cmp r2,#0x0
+    jmpr cc_NZ,.uml2
+    mov r8,r9
+    mov r9,#0x0
+    jmpr cc_UC,.uml3
+
+.uml2: shl r11,r2
+    neg r2
+    shr r10,r2
+    or r11,r10
+    mov r10,r9
+    shr r9,r2
+    shr r8,r2
+    neg r2
+    shl r10,r2
+    or r8,r10
+    
+.uml3: mov MDH,r9
+    mov MDL,r8
+    divlu r11
+    mov r8,MDL
+    mov r11,[r0+]
+    mov r10,[r0+]
+    mulu r8,r11
+    mov r9,MDL
+    mulu r8,r10
+    add r9,MDH
+    mov r8,MDL
+    jmpr cc_NC,.uml4
+    sub r8,r10
+    subc r9,r11
+
+.uml4: sub r8,[r0+]
+    subc r9,[r0+]
+    jmpr cc_ULE,.uml5
+    sub r8,r10
+    subc r9,r11
+    
+.uml5: neg r9
+    neg r8
+    subc r9,#0x0
+    mov r5,r9
+    mov r4,r8
+    mov r2,[r0+]
+       
+
+
+
+#ifdef __xc16xL__   
+   rets
+#else 
+   ret
+#endif   
+
+
+;Function For Logical Shift right  in SI mode (32 bits)   
+
+.global ___lshrsi3
+___lshrsi3:
+
+
+
+	JMPr	cc_UC,.l0003
+.l0002:
+SHR	R8,#1
+	BMOV	R8.15,R9.0
+	SHR	R9,#1
+.l0003:
+	CMPD1	R10,#0
+	JMPr	cc_NE,.l0002
+
+;mov r11,r9
+;shr r8,r10
+;shr r9,r10
+
+
+
+;neg r10
+;shl r11,r10
+;or r8,r11
+mov r4,r8
+mov r5,r9
+
+#ifdef __xc16xL__   
+   rets
+#else 
+   ret
+#endif   
+
+
+;Function For Arithmatic Shift left  in SI mode (32 bits)   
+
+
+.global ___ashlsi3
+___ashlsi3:
+
+	JMPr	cc_UC,.l0013
+.l0012:
+;SHL	R8,#1
+;	BMOV	R9.0,R8.15
+;	SHL	R9,#1
+add r8,r8
+addc r9,r9
+.l0013:
+	CMPD1	R10,#0
+	JMPr	cc_NE,.l0012
+
+
+;mov r11,r8
+;shl r8,r10
+;shl r9,r10
+;neg r10
+;shr r11,r10
+;or r9,r11
+mov r4,r8
+mov r5,r9
+
+
+
+#ifdef __xc16xL__   
+   rets
+#else 
+   ret
+#endif   
+
+
+;Function For Arithmatic Shift right  in SI mode (32 bits)   
+#if 0
+.global ___ashrsi3
+___ashrsi3:
+
+
+
+cmp r10,#0
+jmpr cc_Z,.rt1
+jbc r10.4,.rt2
+mov r11,r9
+shr r8,r10
+ashr r9,r10
+neg r10
+shl r11,r10
+or r8,r11
+jmpr cc_UC,.rt1
+
+.rt2: 
+mov r8,r9
+ashr r9,#0x0f
+ashr r8,r10
+
+.rt1:
+mov r4,r8
+mov r5,r9
+
+#ifdef __xc16xL__
+	rets
+#else
+	ret
+#endif	
+#endif
+
+.global ___ashrsi3
+___ashrsi3:
+
+
+
+	JMPr	cc_UC,.l1003
+.l1002:
+SHR	R8,#1
+	BMOV	R8.15,R9.0
+	ASHR	R9,#1
+.l1003:
+	CMPD1	R10,#0
+	JMPr	cc_NE,.l1002
+
+;mov r11,r9
+;shr r8,r10
+;shr r9,r10
+
+
+
+;neg r10
+;shl r11,r10
+;or r8,r11
+mov r4,r8
+mov r5,r9
+
+#ifdef __xc16xL__   
+   rets
+#else 
+   ret
+#endif   
diff -Naur gcc-4.2-20060218orig/gcc/config/xc16x/predicates.md gcc-4.2-20060218/gcc/config/xc16x/predicates.md
--- gcc-4.2-20060218orig/gcc/config/xc16x/predicates.md	1970-01-01 05:30:00.000000000 +0530
+++ gcc-4.2-20060218/gcc/config/xc16x/predicates.md	2006-03-03 17:13:37.727474272 +0530
@@ -0,0 +1,77 @@
+;; Predicate definitions for Infineon xc16x.
+;; Copyright (C) 2006 Free Software Foundation, Inc.
+;; 
+;; Contributed by Shrirang Khisti On behalf of KPIT Cummins Infosystems Ltd.
+;; This file is part of GCC.
+;; 
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+;; Boston, MA 02110-1301, USA.
+
+;; Return true if OP is a valid source operand for an integer move
+;; instruction.
+
+(define_predicate "general_operand_src"
+  (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem")
+{
+ return general_operand_src1(op,mode);
+
+})
+
+;; Return true if OP is a valid destination operand for an integer
+;; move instruction.
+
+(define_predicate "general_operand_dst_byte"
+  (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem")
+{
+    return general_operand_dst_byte1 (op, mode);
+})
+
+;; Likewise the second operand.
+
+(define_predicate "general_call_operand"
+  (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem")
+{
+
+  return general_call_operand1 (op, mode);
+})
+
+;; Return true if OP is a suitable first operand for a general
+;; arithmetic insn such as "add".
+
+(define_predicate "general_operand_dst_mem"
+  (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem")
+{
+
+  return general_operand_dst_mem1 (op, mode);
+})
+
+;; Check that an operand is either a register or an unsigned 4-bit
+;; constant.
+
+(define_predicate "general_operand_src_mem"
+  (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem")
+{
+ return general_operand_src_mem1 (op, mode);
+
+})
+
+;; Check that an operand is either a register or an unsigned 4-bit
+;; constant.
+
+(define_predicate "general_operand_dst"
+  (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem")
+{
+ return general_operand_dst1 (op, mode);
+})
diff -Naur gcc-4.2-20060218orig/gcc/config/xc16x/t-xc16x gcc-4.2-20060218/gcc/config/xc16x/t-xc16x
--- gcc-4.2-20060218orig/gcc/config/xc16x/t-xc16x	1970-01-01 05:30:00.000000000 +0530
+++ gcc-4.2-20060218/gcc/config/xc16x/t-xc16x	2006-03-03 17:11:52.016544776 +0530
@@ -0,0 +1,16 @@
+LIB1ASMSRC = xc16x/lib1funcs.asm
+LIB1ASMFUNCS =  ___divsi3 ___udivsi3 ___modsi3 ___umodsi3   _popcountdi2  ___lshrsi3 ___ashlsi3 __main __ashrsi3 
+ 
+TARGET_LIBGCC2_CFLAGS = -DDF=SF
+FPBIT = fp-bit.c
+
+fp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#define FLOAT' >fp-bit.c
+	cat $(srcdir)/config/fp-bit.c >>fp-bit.c        
+
+MULTILIB_OPTIONS = mlarge/msmall
+MULTILIB_DIRNAMES = xc16xl xc16xs
+LIBGCC = stmp-multilib
+INSTALL_LIBGCC = install-multilib
+
+
diff -Naur gcc-4.2-20060218orig/gcc/config/xc16x/xc16x.c gcc-4.2-20060218/gcc/config/xc16x/xc16x.c
--- gcc-4.2-20060218orig/gcc/config/xc16x/xc16x.c	1970-01-01 05:30:00.000000000 +0530
+++ gcc-4.2-20060218/gcc/config/xc16x/xc16x.c	2006-03-03 17:14:01.076924616 +0530
@@ -0,0 +1,1785 @@
+/*Subroutines used for code generation on the Infineon xc16x cpu.
+   Copyright (C)  2006
+   Free Software Foundation, Inc.
+
+   Contributed by Shrirang Khisti on behalf of KPIT Cummins Infosystems Ltd.
+
+   This file is part of GCC.
+
+   GGC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 2, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING.  If not, write to
+   the Free Software Foundation, 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "rtl.h"
+#include "tree.h"
+#include "regs.h"
+#include "hard-reg-set.h"
+#include "real.h"
+#include "insn-config.h"
+#include "conditions.h"
+#include "output.h"
+#include "insn-attr.h"
+#include "flags.h"
+#include "recog.h"
+#include "expr.h"
+#include "function.h"
+#include "optabs.h"
+#include "toplev.h"
+#include "c-pragma.h"
+#include "tm_p.h"
+#include "ggc.h"
+#include "target.h"
+#include "target-def.h"
+static void xc16x_output_function_prologue (FILE *file, HOST_WIDE_INT size);
+static void xc16x_output_function_epilogue (FILE *file, HOST_WIDE_INT size);
+static const char *byte_reg (rtx x, int a);
+static tree xc16x_handle_fndecl_attribute (tree *node, tree name,tree args ATTRIBUTE_UNUSED,int flags ATTRIBUTE_UNUSED, bool *no_add_attrs);
+static tree xc16x_handle_fndecl1_attribute (tree *node, tree name,tree args ATTRIBUTE_UNUSED,int flags ATTRIBUTE_UNUSED, bool *no_add_attrs);
+static int xc16x_interrupt_function_p (tree func);
+static int xc16x_disable_interrupt_function_p (tree func);
+static int xc16x_interrupt_noreturn_function_p (tree func);
+static int xc16x_using_regno_function_p (tree func);
+static void xc16x_insert_attributes (tree node, tree *attributes);
+static int xc16x_far_data(tree decl);
+int single_one_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED);
+int single_zero_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED);
+void xc16x_ext_libcall(rtx symref);
+
+
+/* Flags regarding pragmas supported specific to xc16x  */
+static int pragma_interrupt_noreturn;
+static int pragma_interrupt_handler;
+static int pragma_disable_intr;
+
+
+int fun_arg;
+/* Word register names  */
+static const char *const names_big[] =
+{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" ,"r8" ,"r9" ,"r10", "r11", "r12" ,"r13" ,"r14","r15" };
+
+/* Byte register names  r0 -r7 are byte addressable  */
+static const char *
+byte_reg (rtx x, int b)
+{
+  static const char *const names_small[] = {
+    "rl0", "rh0", "rl1", "rh1", "rl2", "rh2", "rl3", "rh3",
+    "rl4", "rh4", "rl5", "rh5", "rl6", "rh6", "rl7", "rh7"
+
+  };
+
+return names_small[REGNO (x) * 2 + b];
+}
+
+
+
+/* Output bset instruction instead of and instruction  */
+const char *
+op_or_insn(rtx *operands)
+{
+  if(single_one_operand(operands[2],QImode))
+   {
+	 switch(INTVAL(operands[2]))
+	  {
+	  case 1: return "bset %T0.0";
+	   break;
+          case 2: return "bset %T0.1";
+	  	   break;
+	  case 4:return "bset %T0.2";
+	  	   break;
+	  case 8:return "bset %T0.3";
+	  	   break;
+	  case 16:return "bset %T0.4";
+	   	  	   break;
+	  case 32:return "bset %T0.5";
+	   	  	   break;
+	  case 64:return "bset %T0.6";
+	  	   break;
+	  case 128:return "bset %T0.7";
+   	  	   break;
+
+          }
+   }
+   else
+   	 return "orb %X0,%X2";
+}
+
+
+/* Output bclr instruction instead of and instruction  */
+const char *
+op_and_insn(rtx * operands)
+{
+  if(single_zero_operand(operands[2],QImode))
+   {
+	 switch(INTVAL(operands[2]))
+	  {
+	  case -2: return "bclr %T0.0";
+	  	   break;
+          case -3: return "bclr %T0.1";
+	  	   break;
+	  case -5:return "bclr %T0.2";
+	  	   break;
+	  case -9:return "bclr %T0.3";
+	  	   break;
+	  case -17:return "bclr %T0.4";
+	   	   break;
+	  case -33:return "bclr %T0.5";
+	   	   break;
+	  case -65:return "bclr %T0.6";
+	  	   break;
+	  case 127:return "bclr %T0.7";
+		   break;
+
+         }
+  }
+  else
+         return "andb %X0,%X2";
+
+}
+
+
+/*  Following function checks weather operand in mode mode has
+    only one bit = 1 in it or not  */
+int
+single_one_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+  if (GET_CODE (operand) == CONST_INT)
+    {
+      /* We really need to do this masking because 0x80 in QImode is
+	 represented as -128 for example.  */
+      if (exact_log2 (INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
+	return 1;
+    }
+
+  return 0;
+}
+
+
+/*  Following function checks weather operand in mode mode has
+    only one bit = 0 in it or not  */
+
+
+int
+single_zero_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+  if (GET_CODE (operand) == CONST_INT)
+    {
+      /* We really need to do this masking because 0x80 in QImode is
+	 represented as -128 for example.  */
+      if (exact_log2 (~INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
+	return 1;
+    }
+
+  return 0;
+}
+/* Output HI mode move instructions  */
+/* Alternative 0  Register / Postincrement to Register
+   Alternative 1  Register to Pre decrement
+   Alternative 2  Immediate to register
+   Alternative 3  Memory to register
+   Alternative 4  Register to memory  */
+
+
+const char * output_movhi_insn(rtx *operands)
+{
+
+      if(which_alternative==0)
+      {
+	   if(TARGET_LARGE)
+           {
+               if(GET_CODE(operands[1])!=REG)
+               {
+	      	    if(REGNO(XEXP(operands[1],0))>1)
+			  /* output_asm_insn("extp #0x2,#0x1",XEXP(operands[1],0));  */
+                          output_asm_insn("extp %f1,#0x1",XEXP(operands[1],0));
+               }
+		     return "mov %T0,%T1";
+	   }
+	   else
+	        return "mov %T0,%T1";
+      }
+      else if(which_alternative<=2)
+      {
+
+	   if(which_alternative==2&&GET_CODE(operands[1])==SYMBOL_REF)
+	 	  return "mov %T0,#SOF:%e1";
+		  return "mov %T0,%T1";
+      }
+
+      else if (which_alternative==3)
+      {
+           if(GET_CODE(XEXP(operands[1],0))==CONST_INT)
+	   {
+	 	 rtx xop[2];
+		 rtx p_no[2];
+		 xop[0]=operands[0];
+		 xop[1]=XEXP(operands[1],0);
+		
+        	 if(TARGET_LARGE)
+		 {
+		 	if(INTVAL(XEXP(operands[1],0))>0xffff)
+	     	        {
+	     	      		 p_no[0]=gen_rtx_CONST_INT(HImode,INTVAL(XEXP(operands[1],0))/0x4000);
+	     	      		 xop[1]=gen_rtx_CONST_INT(HImode,INTVAL(XEXP(operands[1],0))%0x4000);
+	     	      		 output_asm_insn("mov %T0,%1",xop);
+	     	      		 output_asm_insn("extp %0,#0x1",p_no);
+	     	      		 output_asm_insn("mov [%T0],%T0",operands);
+	     	      		 return "";
+	                }
+	     	}
+	        output_asm_insn("mov %T0,%1",xop);
+	        output_asm_insn("mov %T0,[%T0]",xop);
+	        return "";
+	   }
+	   if(TARGET_LARGE)
+	   {
+	        if(GET_CODE(XEXP(operands[1],0))==SYMBOL_REF||GET_CODE(XEXP(operands[1],0))==CONST)
+	        {
+
+	             /* Following can be used for checking constant
+	                if(!CONSTANT_POOL_ADDRESS_P(operands[1]))  */
+		              
+		     if(GET_CODE(XEXP(operands[1],0))==CONST) 
+		     {
+			     output_asm_insn("extp #pag: %T1,#0x1",operands);
+
+			     return "mov %T0,pof:%T1";
+				
+		     } 
+		     
+                     if(SYMBOL_REF_FLAGS(XEXP(operands[1],0))&1)
+		             return "mov %T0,#SOF:%T1";
+ 		     else   
+		             output_asm_insn("extp #pag: %T1,#0x1",operands);
+
+		     return "mov %T0,pof:%T1";
+
+	       }
+	       else
+	       {
+
+	             if(GET_CODE(XEXP(operands[1],0))!=PLUS&&REGNO(XEXP(operands[1],0))!=0)
+		     {
+        		     output_asm_insn("extp %d1,#0x1",operands);
+		     }
+
+
+	            return "mov	%e0,%e1";
+
+ 	      }
+
+	 }
+	 else
+	      return "mov %T0,%T1";
+
+
+      }
+      else if(which_alternative==4)
+      {
+
+	 if(GET_CODE(XEXP(operands[0],0))==CONST_INT)
+	 {
+	        rtx p_no[2];
+	        rtx xop[2];
+	        xop[1]=operands[1];
+	        xop[0]=XEXP(operands[0],0);
+	        if(TARGET_LARGE)
+	     	{
+	            if(INTVAL(XEXP(operands[0],0))>0xffff)
+	     	    {
+	     		 p_no[0]=gen_rtx_CONST_INT(HImode,INTVAL(XEXP(operands[0],0))/0x4000);
+	     		 output_asm_insn("mov [-r0],%f1",xop);
+	     	 	 xop[0]=gen_rtx_CONST_INT(HImode,INTVAL(XEXP(operands[0],0))%0x4000);
+	     		 output_asm_insn("mov %f1,%0",xop);
+	     		 output_asm_insn("extp %0,#0x1",p_no);
+	     		 output_asm_insn("mov [%f1],%T1",operands);
+	     		 output_asm_insn("mov %f1,[r0+]",xop);
+	     		 return "";
+	            }
+	        }
+	       	         output_asm_insn("mov [-r0],%f1",xop);
+	     		 output_asm_insn("mov %f1,%0",xop);
+	  		 output_asm_insn("mov [%f1],%T1",xop);
+                 	 output_asm_insn("mov %f1,[r0+]",xop);
+
+
+                 	 return "";
+	 }
+	 if(TARGET_LARGE)
+	 {
+	     if(GET_CODE(XEXP(operands[0],0))==SYMBOL_REF||GET_CODE(XEXP(operands[0],0))==CONST)
+	     {
+
+	       /* if(!MEM_SCALAR_P(operands[0])||SYMBOL_REF_FLAGS(XEXP(operands[0],0))!=2)
+                  if(!CONSTANT_POOL_ADDRESS_P(XEXP(operands[0],0)))  */
+
+ 	          output_asm_insn("extp #pag: %T0,#0x1",operands);
+ 	          return "mov pof:%T0,%T1";
+             }
+
+             else
+             {
+	          if(GET_CODE(XEXP(operands[0],0))!=PLUS&&REGNO(XEXP(operands[0],0))!=0)
+	          {
+	      	     output_asm_insn("extp %d0,#0x1",operands);
+        	  }
+		     return "mov	%e0,%e1";
+
+            }
+         }
+         else
+             return "mov %T0,%T1";
+
+   }
+}
+/* Output call instructions  */
+
+const char *
+output_call_insn(rtx *operands)
+{
+  char str[20];
+
+
+
+  if(TARGET_LARGE)
+  {
+     if(REG_P(operands[1]))  /*Indirect Call*/
+     {
+        rtx  label = gen_label_rtx();
+
+        output_asm_insn("push csp",operands);
+        output_asm_insn("calli cc_UC,[%1]",operands);
+        return " ";
+
+     }
+     else if (REG_P(XEXP(operands[1],0)))  /*Indirect Call*/
+     {
+         rtx  label = gen_label_rtx();
+	 output_asm_insn("push csp",operands);
+         output_asm_insn("calli cc_UC,%1",operands);
+         return " ";
+     }
+     else
+     {
+	  if(strcmp((XSTR(XEXP(operands[1],0),0)),"__main")==0)
+	  return "";
+
+          return "calls #SEG:%1,#SOF:%1";
+
+          return"";
+     }
+  }
+
+  else   /* Call for Tiny Model  */
+  {
+     if (GET_CODE(operands[1]) == MEM &&
+                 REG_P(XEXP(operands[1],0)))
+          return "calli cc_UC,%1";
+     else if (REG_P (operands[1]))
+          return "calli cc_UC,[%1]";            /* Indirect Call  */
+     else
+
+     if(GET_CODE(XEXP(operands[1],0))!=PLUS)
+    	  return "calla cc_UC,%1";
+     else
+    	  return " ";
+   }
+}
+
+
+
+/* Output call instructions  */
+
+const char *
+output_call_insn1(rtx *operands)
+{
+  if(TARGET_LARGE)                    /* Large target Calls  */
+   {
+    if(REG_P(operands[0]))
+       {
+         output_asm_insn("push csp",operands);
+         output_asm_insn("calli cc_UC,[%0]",operands);
+         return " ";
+
+       }
+    else if (REG_P(XEXP(operands[0],0)))    /* Indirect Call  */
+       {
+         rtx  label = gen_label_rtx();
+   	 output_asm_insn("push csp",operands);
+         output_asm_insn("calli cc_UC,%0",operands);
+         return " ";
+
+       }
+   else
+       {
+         if(strcmp((XSTR(XEXP(operands[0],0),0)),"__main")==0)
+ 	        return " ";
+         else
+        	 return "calls #SEG:%0 ,#SOF:%0" ;
+
+	return "";
+       }
+   }
+   else   /* Call for tiny Model  */
+   {
+       if (GET_CODE(operands[0]) == MEM &&
+	        REG_P(XEXP(operands[0],0)))
+           return "calli cc_UC,%0";
+       else if (REG_P (operands[0]))
+           return "calli cc_UC,[%0]";
+       else
+       {
+       	   if(strcmp((XSTR(XEXP(operands[0],0),0)),"__main")==0)
+        	return " ";
+           else
+	        return "calla cc_UC, %0";
+
+       }
+   }
+}
+
+/* Output cmppsi instruction  */
+const char *
+output_cmppsi_insn(rtx *operands)
+{
+       rtx label=gen_label_rtx();
+
+
+       if(which_alternative==0)
+       {
+    	  output_asm_insn("cmp %f0,%f1",operands);
+	  output_asm_insn("jmpr cc_NE,%l0",&label);
+	  output_asm_insn("cmp %e0,%e1",operands);
+	  (*targetm.asm_out.internal_label) (asm_out_file,"L",CODE_LABEL_NUMBER(label));
+       }
+
+
+      else if(which_alternative==1)
+      {
+	  output_asm_insn("cmp %f0,%e1",operands);
+	  output_asm_insn("jmpr cc_NE,%l0",&label);
+	  output_asm_insn("cmp %e0,%f1",operands);
+	  (*targetm.asm_out.internal_label) (asm_out_file,"L",CODE_LABEL_NUMBER(label));
+
+      }
+
+      return " ";
+
+}
+
+
+
+/* Output move instruction for Pointers in large memory model  */
+/*
+Alternative:0 Register to Register
+            1 Immediate to Register
+            2 Register to memory
+            3 Memory to Register
+            4 Register to Predecrement  */
+
+const char *
+output_movpsi_insn(rtx *operands)
+{
+  switch(which_alternative)
+  {
+       /* Register to Register move  */
+       case 0:
+       {
+	     if(REGNO(operands[1])==1)
+	     {
+                 /* output_asm_insn("mov %f0,#0x2",operands);  */
+	         output_asm_insn("mov %f0,DPP2",operands);
+    	         output_asm_insn("mov %e0,%e1",operands);
+
+	         return "";
+	     }
+	     else
+	     {
+		 if((REGNO(operands[1])-REGNO(operands[0]))==1)
+		 {
+		     output_asm_insn("mov %e0,%e1",operands);
+	             return "mov %f0,%f1";
+		 }
+		 else
+		 {
+		     output_asm_insn("mov %f0,%f1",operands);
+		     return "mov %e0,%e1";
+		 }
+	     }
+	     break;
+       }
+
+       /*Immediate to register move  */
+       case 1:
+       {
+  	   if(GET_CODE(operands[1])==SYMBOL_REF||GET_CODE(operands[1])==CONST)
+	   {
+	      if(GET_CODE(operands[1])==SYMBOL_REF)
+	      {
+	           /*tree decl;
+	             if(SYMBOL_REF_DECL (operands[1]))
+
+	             decl = SYMBOL_REF_DECL (operands[1]);
+
+	             if(TREE_CODE (decl) != VAR_DECL && TREE_CODE (decl)!=STRING_CST)*/
+	 	  if(SYMBOL_REF_FLAGS(operands[1])&1)
+	          {
+
+	              output_asm_insn ("mov %e0,#SOF:%e1",operands);
+                      return " ";
+	          }
+	          else
+	          {
+	              output_asm_insn ("mov %f0,#PAG:%e1",operands);
+		      output_asm_insn ("mov %e0,#POF:%e1",operands);
+		      return "";
+		  }
+
+
+              }
+              else
+              {
+		   output_asm_insn ("mov %f0,#PAG:%e1",operands);
+	           output_asm_insn ("mov %e0,#POF:%e1",operands);
+              }
+              return " ";
+	  }
+	  else
+	  {
+	      if(INTVAL(operands[1])!=0)
+	      {
+                 /* output_asm_insn ("mov %f0,DPP2",operands); */
+		   rtx op[3];
+		   op[0]=operands[0];
+		   op[1]=gen_rtx_CONST_INT(HImode,INTVAL(operands[1])/0x4000);
+		   if(GET_CODE(operands[1])==LABEL_REF)
+		   {
+		       output_asm_insn("mov %f0,#PAG:%f1",operands);
+		       return "mov %e0,#POF:%e1";
+		   }
+		   output_asm_insn ("mov %f0,#0x3",op);
+		   return "mov %e0,%f1";
+	       }
+	       else
+	       {
+	           output_asm_insn ("mov %f0,#0x0",operands);
+	           return "mov %e0,#0x0";
+	       }
+	  }
+
+      }
+
+     /* Register to memory move  */
+      case 2:
+      {
+         if(GET_CODE(XEXP(operands[0],0))==SYMBOL_REF||GET_CODE(XEXP(operands[0],0))==CONST)
+         {
+	     output_asm_insn("extp #pag:%e0,#0x2",operands);
+	     if(REGNO(operands[1])==1)
+		   return "mov pof:%f0,DPP2\n\tmov    pof:%e0,%e1";
+	     else
+		   return "mov pof:%f0,%f1\n\tmov    pof:%e0,%e1";
+	 }
+
+         else
+         {
+             if(GET_CODE(XEXP(operands[0],0))==PLUS)
+	     {
+	        if(REGNO(XEXP(XEXP(operands[0],0),0))!=1&&REGNO(XEXP(XEXP(operands[0],0),0))!=0)
+	        {
+                     output_asm_insn("extp %Y0,#0x2",operands);
+                }
+	     }
+	     else
+	     {
+	         output_asm_insn("extp %d0,#0x2",operands);
+	     }
+	     return "mov	%f0,%f1\n\tmov	%e0,%e1";
+ 	 }
+      }
+	 /* Memory to register move */
+      case 3:
+      {
+	 if(GET_CODE(XEXP(operands[1],0))==SYMBOL_REF||GET_CODE(XEXP(operands[1],0))==CONST)
+ 	 {
+             /* Original */
+ 	     output_asm_insn("extp #pag:%e1,#0x2",operands);
+             return "mov %f0,pof:%f1\n\tmov    %e0,pof:%e1";
+
+ 	 }
+ 	 else
+         {
+
+	     if(GET_CODE(XEXP(operands[1],0))==PLUS)
+	     {
+	        if(REGNO(XEXP(XEXP(operands[1],0),0))!=1&&REGNO(XEXP(XEXP(operands[1],0),0))!=0)
+	        {
+
+    		   output_asm_insn("extp %Y1,#0x2",operands);
+		   if(REGNO(XEXP(XEXP(operands[1],0),0))==(REGNO(operands[0])+1))  
+               	      return "mov  %e0,%e1\n\tmov  %f0,%f1";
+   
+		}
+	     }
+	     else
+	     {
+    	         output_asm_insn("extp %d1,#0x2",operands);
+	     }
+	     return "mov	%f0,%f1\n\tmov	%e0,%e1";
+
+ 	}
+
+      }
+      case 4: return "mov	%e0,%f1\n\tmov	%e0,%e1";
+
+  }
+
+
+}
+
+
+/* Output addition specially for pointers for Large target  */
+
+const char *
+output_addpsi_insn(rtx insn1,rtx *operands,int flag)
+{
+ rtx xop[3];
+ switch(which_alternative)
+ {
+ case 0:
+ {
+  if(flag==0)
+  {
+      if(REGNO(operands[2])<2)
+      {
+          output_asm_insn("add %e0,%e2",operands);
+
+	  return "mov %f0,DPP2";
+      }
+      else
+      {
+      	  output_asm_insn("add %e0,%e2",operands);
+
+	  return "addc %f0,%f2";
+      }
+   }
+
+
+  else if(flag==1)
+  {
+     if(REGNO(operands[2])<2)
+     {
+       	output_asm_insn("sub %e0,%e2",operands);
+
+   	return "mov %f0,DPP2";
+     }
+     else
+     {
+        output_asm_insn("sub %e0,%e2",operands);
+
+   	return "sub %f0,%f2";
+     }
+
+  }
+ }
+ case 1:
+  {
+     xop[0]=operands[0];
+     xop[2]=gen_rtx_CONST_INT ( VOIDmode,INTVAL (operands[2]) & 0xffff);
+     if(flag==0)
+            output_asm_insn("add %e0,%f2",xop);
+     else if(flag==1)
+            output_asm_insn("sub  %e0,%f2",xop);
+     return " ";
+ }
+
+
+ }
+}
+
+
+/*  Following function will output a particular operand to target assembly file  */
+/*
+Codes used:
+X: Used to output  registers for QI mode
+T: Used for outputting HI mode registers
+e: Used in SI / SF mode
+f: Used in SI / SF mode .In this case register with next immediate high number is printed as operand
+c: In case of [Rn] used to print operand as [Rn+1] used in SI/Sf modes
+d: In case of [Rn] used to print operand as Rn+1 used in SI/Sf modes
+D: In case of [Rn] used to print operand as Rn used in SI/Sf modes
+Y: in case of [Rn+#0xaaa] used to print operand as Rn+1 used in SI/Sf modes  */
+
+void print_operand (FILE *file, rtx x, int code)
+{
+  switch(code)
+    {
+     case 'X':
+     	if (GET_CODE (x) == REG)
+     	{
+	     if(REGNO(x)<=7)
+    	     	fprintf (file, "%s", byte_reg (x, 0));
+             else
+    	        fprintf (file, "%s", names_big[REGNO (x)]);
+        }
+        else if(GET_CODE(x)==CONST_INT)
+    	    fprintf(file,"#0x%x",(unsigned char)INTVAL(x));
+        else
+	goto def;
+	break;
+
+    case 'T':
+        if (GET_CODE (x) == REG)
+            fprintf (file, "%s", names_big[REGNO (x)]);
+        else
+            goto def;
+        break;
+
+   case 'e':
+        switch (GET_CODE (x))
+   	{
+   	case REG:
+   	    fprintf (file, "%s", names_big[REGNO (x)]);
+            break;
+
+   	case MEM:
+            print_operand (file, x, 0);
+    	    break;
+
+        case CONST_INT:
+   	    fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
+   	    break;
+
+        case CONST_DOUBLE:
+	{
+	    long val;
+	    REAL_VALUE_TYPE rv;
+	    REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
+	    REAL_VALUE_TO_TARGET_SINGLE (rv, val);
+	    fprintf (file, "#0x%x", ((val >> 16) & 0xffff));
+	    break;
+	 }
+   	case SYMBOL_REF:
+   	case    LABEL_REF:
+   	case CONST:
+   	    print_operand_address(file,x);
+   	break;
+   	default:
+   	     abort ();
+   	break;
+   	}
+    break;
+    case 'f':
+	switch (GET_CODE (x))
+   	{
+   	case REG:
+   	    fprintf (file, "%s", names_big[REGNO (x) + 1]);
+   	    break;
+
+   	case MEM:
+   	    x = adjust_address (x, HImode, 2);
+   	    print_operand (file, x, 0);
+   	    break;
+
+   	case CONST_INT:
+   	    fprintf (file, "#%ld", INTVAL (x) & 0xffff);
+	    break;
+
+        case CONST_DOUBLE:
+        {
+	    long val;
+	    REAL_VALUE_TYPE rv;
+	    REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
+	    REAL_VALUE_TO_TARGET_SINGLE (rv, val);
+	    fprintf (file, "#0x%x", (val & 0xffff));
+	    break;
+        }
+
+   	case SYMBOL_REF:
+	case LABEL_REF:
+	case CONST:
+ 	    print_operand_address(file,x);
+            break;
+   	default:
+   	    abort ();
+   	}
+        break;
+    case 'i':
+    {
+	fprintf (file, "%ld", INTVAL (x) & 0xffff);
+	break;
+    }
+    case 'c':
+    {
+        int reg_no;
+
+	fprintf(file,"[%s]",names_big[REGNO (XEXP(x,0)) + 1]);
+	break;
+    }
+
+    case 'd':
+    {
+        int reg_no;
+
+        fprintf(file,"%s",names_big[REGNO (XEXP(x,0)) + 1]);
+        break;
+    }
+
+	/* To output reg contained in mem in Large Taregt option*/
+    case 'D':
+    {
+	 int reg_no;
+	 fprintf(file,"%s",names_big[REGNO (XEXP(x,0))]);
+	 break;
+    }
+    case 'Y':
+    {
+         int reg_no;
+	 fprintf(file,"%s",names_big[REGNO (XEXP(XEXP(x,0),0)) + 1]);
+	 break;
+    }
+    case 's':
+    	 fprintf(file,"%d",INTVAL(x));
+         break;
+    default:
+    def:
+    switch (GET_CODE (x))
+    {
+   	case REG:
+
+   	  switch (GET_MODE (x))
+          {
+   	    case QImode:
+
+   	       fprintf (file, "%s", byte_reg (x, 0));
+   	       break;
+
+            case HImode:
+   	    case SImode:
+   	    case PSImode:
+   	    case SFmode:
+   	       fprintf (file, "%s", names_big[REGNO (x)]);
+   	       break;
+
+
+   	    default:
+   	      abort ();
+   	  }
+   	    break;
+
+   	    case MEM:
+   	    {
+   	       rtx addr = XEXP (x, 0);
+
+   	       if(GET_CODE(addr)==SYMBOL_REF||GET_CODE(addr)==LABEL_REF||GET_CODE(addr)==CONST)
+   	          output_address (addr);
+   	       else
+   	       {
+		  fprintf (file, "[");
+		  output_address (addr);
+		  fprintf (file, "]");
+	       }
+
+
+   	    }
+   	    break;
+
+   	case CONST_INT:
+
+   	case CONST:
+   	case LABEL_REF:
+        case SYMBOL_REF:
+   	  fprintf (file, "#");
+   	  print_operand_address (file, x);
+   	  break;
+
+        case CONST_DOUBLE:
+	{
+	    long val;
+	    REAL_VALUE_TYPE rv;
+	    REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
+	    REAL_VALUE_TO_TARGET_SINGLE (rv, val);
+	    fprintf (file, "#0x%x", (unsigned short)val);
+	    break;
+	}
+   	default:
+   	  break;
+	}
+ }
+}
+
+
+void print_operand_address (FILE *file, rtx addr)
+{
+
+   switch (GET_CODE (addr))
+     {
+      case REG:
+       fprintf (file, "%s", names_big[REGNO (addr)]);
+       break;
+
+      case PRE_DEC:
+       fprintf (file, "-%s", names_big[REGNO (XEXP (addr, 0))]);
+       break;
+
+      case POST_INC:
+       fprintf (file, "%s+", names_big[REGNO (XEXP (addr, 0))]);
+       break;
+
+      case PLUS:
+
+       if (GET_CODE (XEXP (addr, 0)) == REG)
+	   {
+	    print_operand_address (file, XEXP (addr, 0));
+	    fprintf (file, "+#");
+	    print_operand_address (file, XEXP (addr, 1));
+	   }
+       else
+	   {
+	    print_operand_address (file, XEXP (addr, 0));
+	    fprintf (file, "+#");
+	    print_operand_address (file, XEXP (addr, 1));
+	   }
+
+      break;
+
+      case CONST_INT:
+       {
+
+	    int n = INTVAL (addr);
+
+	    n = (int) (short) n;
+
+	    fprintf (file, "0x%x", (unsigned short)n);
+	    break;
+       }
+
+      default:
+       output_addr_const (file, addr);
+      break;
+   }
+
+}
+
+
+
+  /* Following function emits the code for function prologue
+     It takes in account weather frame pointer is needed or not
+     Also among other activities it will check for certain attributes
+     and genrate that particular code. Also it will generate code
+     different related to different target options  */
+
+
+
+
+static void
+xc16x_output_function_prologue (FILE *file, HOST_WIDE_INT size)
+{
+  register int regno;
+  int val;
+
+
+	if(xc16x_disable_interrupt_function_p(current_function_decl))
+	    fprintf(file,"\t bclr psw.11\n");
+	if(xc16x_interrupt_noreturn_function_p(current_function_decl))
+            return;
+
+/* Following statement will round up the value to nearest big even number  */
+	size = (size + 1) & ~1 ;
+
+
+
+/* Following code checks frame pointer requirement  */
+	if(frame_pointer_needed)
+	{
+         /* Save the frame pointer  */
+            fprintf(file,"\t mov  [-r%d],r%d\n",STACK_POINTER_REGNUM,FRAME_POINTER_REGNUM);
+         /* Set new frame pointer  */
+            if(!xc16x_using_regno_function_p(current_function_decl))
+               fprintf(file,"\t mov  r%d,r%d\n",FRAME_POINTER_REGNUM,STACK_POINTER_REGNUM);
+
+	}
+
+
+
+/* Here  attribute relate functions should be called to check for the existance of a
+   certain attribute and generate the code correspondingly  */
+
+/* if (xc16x_using_regno_function_p (current_function_decl))
+ fprintf(file,"%d",fun_arg);  */
+
+
+/* switch the register bank with provided along with attribute  */
+	if(xc16x_using_regno_function_p(current_function_decl))
+	{
+	   val=TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (lookup_attribute ("using_regno",
+	                                                  DECL_ATTRIBUTES (current_function_decl)))));
+	   fprintf(file,"\t mov %d,r0 \n",val);
+	   fprintf(file,"\t scxt cp,#%d \n",val);
+	   /* fprintf(file,"\t reti \n"); */
+	   fprintf(file,"\t mov  r%d,r%d\n",FRAME_POINTER_REGNUM,STACK_POINTER_REGNUM);
+        }
+
+/* Push DPP0 on the stack  */
+	if(xc16x_interrupt_function_p(current_function_decl))
+	{
+	   if(!TARGET_NO_DPPSAVE)
+	      fprintf(file,"push DPP0\n");
+	}
+
+
+	if (size<0xffff)
+	    fprintf(file,"\t sub  r%d,#%d\n",STACK_POINTER_REGNUM,size+(0));
+	else
+	    error("Stack size is greater that 64K");		
+
+	if(xc16x_interrupt_function_p(current_function_decl)&&!xc16x_using_regno_function_p(current_function_decl))
+        {
+           for (regno = 2; regno < FIRST_PSEUDO_REGISTER; regno++)
+	        if (regs_ever_live[regno])
+                    fprintf(file,"\tpush r%d\n",(regno));
+
+	}
+	else
+	{
+	    for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
+	        if (regs_ever_live[regno] && !call_used_regs[regno])
+                /* fprintf(file,"\tmov [-r%d],r%d\n",STACK_POINTER_REGNUM,(regno)); */
+		fprintf(file,"\t push r%d \n",(regno));
+	}
+}
+
+
+
+
+static void
+xc16x_output_function_epilogue (FILE *file, HOST_WIDE_INT size)
+{
+
+     register int regno;
+
+     if(xc16x_disable_interrupt_function_p(current_function_decl))
+	       fprintf(file,"\t bset psw.11\n");
+
+
+
+     /* If function has been provided with function_noreturn it wont generate any epilogue  */
+
+
+     if(xc16x_interrupt_noreturn_function_p(current_function_decl))
+     		return;
+
+     size = (size + 1) & ~1 ;
+
+     if(xc16x_interrupt_function_p(current_function_decl)&&!xc16x_using_regno_function_p(current_function_decl))
+     {
+       	for (regno = FIRST_PSEUDO_REGISTER-1; regno >=2; regno--)
+             if (regs_ever_live[regno] )
+       		    fprintf(file,"\tpop r%d\n",(regno));
+     }
+     else
+     {
+        for (regno = FIRST_PSEUDO_REGISTER-1; regno >=0; regno--)
+	     if (regs_ever_live[regno] && !call_used_regs[regno])
+             /* fprintf(file,"\tmov r%d,[r%d+]\n",(regno),STACK_POINTER_REGNUM); */
+	          fprintf(file,"\t pop r%d \n",(regno));
+     }
+
+
+    if (size)
+   	    fprintf(file,"\t add  r%d,#%d\n",STACK_POINTER_REGNUM,size+(0));
+
+
+
+
+     /* Following function checks weather function is interrupt handler
+        If so it will further check for target option -mno-dppsave
+        if option is absent it will pop DPPO  */
+
+
+     if(xc16x_interrupt_function_p(current_function_decl))
+     {
+	    if(!TARGET_NO_DPPSAVE)
+	      fprintf(file,"pop DPP0\n");
+     }
+
+
+    /* Following function checks weather using_regno attribute is provided
+       for the current function if so it will pop cp and emit reti
+       instruction  */
+
+
+    if(xc16x_using_regno_function_p(current_function_decl))
+    {
+       fprintf(file,"\t pop cp \n");
+       if(frame_pointer_needed)
+       fprintf(file,"\t mov  r%d,[r%d+]\n",FRAME_POINTER_REGNUM,STACK_POINTER_REGNUM);
+       fprintf(file,"\t reti \n");
+
+       return;
+    }
+
+    /* Else  it will emit only reti instruction  */
+    else if(xc16x_interrupt_function_p(current_function_decl))
+    {
+        if(frame_pointer_needed)
+        	fprintf(file,"\t mov  r%d,[r%d+]\n",FRAME_POINTER_REGNUM,STACK_POINTER_REGNUM);
+	fprintf(file,"\t reti \n");
+	return;
+
+    }
+
+    if(frame_pointer_needed)
+    {
+        /* Restore the frame pointer  */
+        fprintf(file,"\t mov  r%d,[r%d+]\n",FRAME_POINTER_REGNUM,STACK_POINTER_REGNUM);
+
+    }
+
+
+     if(TARGET_LARGE)
+   					 /* Changed from rets to ret  */
+        fprintf(file,"rets\n");
+     else
+        fprintf(file,"ret\n");
+
+
+
+}
+
+
+
+  /* Following structure is regarding attribute specification
+   Important fields are
+   name : name of the attribute to be supported
+   min-len,max len : length of arguments passed with attributes
+   handler : function checking validity */
+
+
+
+const struct attribute_spec xc16x_attribute_table[] =
+{
+     /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler }*/
+     { "interrupt_handler", 0, 0, true,  false, false, xc16x_handle_fndecl_attribute },
+     { "disable_intr",           0, 0, true,  false, false, xc16x_handle_fndecl_attribute },
+     { "interrupt_noreturn",           0, 0, true,  false, false, xc16x_handle_fndecl_attribute },
+     { "using_regno",           1, 1, true,  false, false, xc16x_handle_fndecl1_attribute },
+     { "far_data",              0,0,true,false,false,NULL},
+     { NULL,                0, 0, false, false, false, NULL }
+};
+
+
+
+/* Handle an attribute requiring a FUNCTION_DECL; arguments as in
+   struct attribute_spec.handler.  */
+
+
+static tree
+xc16x_handle_fndecl_attribute (tree *node, tree name,
+			       tree args ATTRIBUTE_UNUSED,
+			       int flags ATTRIBUTE_UNUSED,
+			       bool *no_add_attrs)
+{
+  if (TREE_CODE (*node) != FUNCTION_DECL)
+    {
+      warning ("`%s' attribute only applies to functions",
+	       IDENTIFIER_POINTER (name));
+      *no_add_attrs = true;
+    }
+
+  return NULL_TREE;
+}
+
+
+/* Handle using_regno attribute and store the value of argument passed with attribute in
+ variable fun_arg  */
+
+
+static tree
+xc16x_handle_fndecl1_attribute (tree *node, tree name,
+			       tree args ATTRIBUTE_UNUSED,
+			       int flags ATTRIBUTE_UNUSED,
+			       bool *no_add_attrs)
+{
+  if (TREE_CODE (*node) != FUNCTION_DECL)
+    {
+      warning ("`%s' attribute only applies to functions",
+	       IDENTIFIER_POINTER (name));
+      *no_add_attrs = true;
+    }
+   fun_arg=TREE_INT_CST_LOW (TREE_VALUE (args));
+  return NULL_TREE;
+}
+
+
+/*  Following function will check weather interrupt_handler attribute is provided
+    or not  */
+
+static int
+xc16x_interrupt_function_p (tree func)
+{
+  tree a;
+
+  if (TREE_CODE (func) != FUNCTION_DECL)
+    return 0;
+
+  a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
+  return a != NULL_TREE;
+}
+
+
+
+/*  Following function will check weather using_regno attribute is provided
+    or not  */
+
+
+static int
+xc16x_using_regno_function_p (tree func)
+{
+  tree a;
+
+ if(xc16x_interrupt_function_p(func))
+  {
+  if (TREE_CODE (func) != FUNCTION_DECL)
+    return 0;
+
+  a = lookup_attribute ("using_regno", DECL_ATTRIBUTES (func));
+  return a != NULL_TREE;
+ }
+  else
+  {
+	/* warning("Missing interrupt handler attribute");  */
+    return 0;
+  }
+}
+
+
+/*  Following function will check weather far attribute is provided or not to variable
+    or not  */
+
+
+static int
+xc16x_far_data(tree decl)
+{
+
+  tree a;
+
+  if (TREE_CODE (decl) != VAR_DECL)
+    return 0;
+
+  a = lookup_attribute ("far_data", DECL_ATTRIBUTES (decl));
+  return a != NULL_TREE;
+
+}
+
+
+
+
+/*  Following function will check weather disable_intr attribute is provided
+    or not  */
+
+
+
+static int
+xc16x_disable_interrupt_function_p (tree func)
+{
+  tree a;
+
+  if (TREE_CODE (func) != FUNCTION_DECL)
+    return 0;
+
+  a = lookup_attribute ("disable_intr", DECL_ATTRIBUTES (func));
+  return a != NULL_TREE;
+}
+
+
+
+/*  Following function will check weather interrupt_noreturn attribute is provided
+    or not */
+
+
+static int
+xc16x_interrupt_noreturn_function_p (tree func)
+{
+  tree a;
+if(xc16x_interrupt_function_p(func))
+{
+
+  if (TREE_CODE (func) != FUNCTION_DECL)
+    return 0;
+
+  a = lookup_attribute ("interrupt_noreturn", DECL_ATTRIBUTES (func));
+  return a != NULL_TREE;
+}
+else
+{
+	/*warning("Missing interrupt handler attribute");*/
+	return 0;
+}
+
+}
+
+/* Generate  attributes for decls from pragmas.  We convert
+   all the pragmas to corresponding attributes. by examining corresponding
+   flags set for corresponding pragmas  */
+
+static void
+xc16x_insert_attributes (tree node, tree *attributes)
+{
+  if (TREE_CODE (node) == FUNCTION_DECL)
+    {
+      if (pragma_interrupt_handler)
+	  {
+	  pragma_interrupt_handler = 0;
+
+	  /* Add an 'interrupt_handler' attribute.  */
+	  *attributes = tree_cons (get_identifier ("interrupt_handler"),
+				   NULL, *attributes);
+	  }
+
+      if (pragma_disable_intr)
+	  	  {
+	  	  pragma_disable_intr = 0;
+
+	    /* Add disable_intr attribute  */
+	  	  *attributes = tree_cons (get_identifier ("disable_intr"),
+	  				   NULL, *attributes);
+	  }
+
+     if (pragma_interrupt_noreturn)
+	 	  {
+	 	  pragma_interrupt_noreturn = 0;
+
+
+	 	  *attributes = tree_cons (get_identifier ("interrupt_noreturn"),
+	 				   NULL, *attributes);
+	  }
+
+
+    }
+}
+
+
+
+/*  Following function is initialization function
+    for pragma disable_intr and will set corresponding flag  */
+
+void xc16x_disable_intr(struct cpp_reader *pfile ATTRIBUTE_UNUSED)
+{
+ pragma_disable_intr=1;
+}
+
+
+/*  Following function is initialization function
+    for pragma interrupt_handler and will set corresponding flag  */
+
+void xc16x_interrupt_handler(struct cpp_reader *pfile ATTRIBUTE_UNUSED)
+{
+ pragma_interrupt_handler=1;
+}
+
+
+/*  Following function is initialization function
+    for pragma interrupt_noreturn and will set corresponding flag  */
+
+
+void xc16x_interrupt_noreturn(struct cpp_reader *pfile ATTRIBUTE_UNUSED)
+{
+ pragma_interrupt_noreturn=1;
+}
+
+
+/* Return true if OP is a valid source operand for an integer move
+   instruction.  */
+
+int
+general_operand_src1 (rtx op, enum machine_mode mode)
+{
+  if (GET_MODE (op) == mode
+      && GET_CODE (op) == MEM
+      && GET_CODE (XEXP (op, 0)) == POST_INC)
+    return 1;
+  return general_operand (op, mode);
+}
+
+
+/* Return true if OP is a valid source operand for an QI mode move
+   instruction.  */
+
+int
+general_operand_dst_byte1 (rtx op, enum machine_mode mode)
+{
+  if(GET_CODE(op)==REG)
+  {
+  if(REGNO(op)>7)
+  return 0;
+  }
+  if (GET_MODE (op) == mode
+      && GET_CODE (op) == MEM
+      && GET_CODE (XEXP (op, 0)) == PRE_DEC)
+    return 1;
+  return general_operand (op, mode);
+}
+
+
+/* Return true if OP is a valid destination operand for an integer move
+   instruction.  */
+
+
+int
+general_operand_dst1 (rtx op, enum machine_mode mode)
+{
+ 
+ if (GET_MODE (op) == mode
+      && GET_CODE (op) == MEM
+      && (GET_CODE (XEXP (op, 0)) == PRE_DEC))
+    return 1;
+  return general_operand (op, mode);
+}
+
+/* Following function will check weather given operand op is valid source
+   operand such that it should not be any indirect base+offset form  */
+
+int
+general_operand_src_mem1 (rtx op, enum machine_mode mode)
+{
+
+  if (GET_CODE (op) == MEM && GET_CODE(XEXP(op,0))==CONST_INT)
+    return 0;
+
+  if (GET_CODE (op) == MEM
+      && ((GET_CODE (XEXP (op, 0))==SYMBOL_REF)||(GET_CODE(XEXP(op,0)))==CONST))
+
+    return 1;
+  return register_operand (op, mode);
+}
+
+
+/* Following function will check weather given operand op is valid destination
+   operand such that it should not be any indirect base+offset form   */
+
+int
+general_operand_dst_mem1 (rtx op, enum machine_mode mode)
+{
+  if (GET_CODE (op) == MEM && GET_CODE(XEXP(op,0))==CONST_INT)
+  return 0;
+  if (GET_CODE (op) == MEM
+      && ((GET_CODE (XEXP (op, 0))==SYMBOL_REF)||(GET_CODE(XEXP(op,0)))==CONST))
+    return 1;
+  return nonmemory_operand (op, mode);
+}
+
+
+int
+general_call_operand1 (rtx op, enum machine_mode mode)
+{
+
+  if(register_operand(op,0))
+      return 1;
+  if (GET_CODE (XEXP (op, 0))==REG||GET_CODE (XEXP (op, 0))==SYMBOL_REF)
+    return 1;
+    return 0;
+  return general_operand (op, mode);
+}
+
+
+void xc16x_ext_libcall(rtx symref)
+{
+  if(strcmp(XSTR(symref,0),"__main")!=0)
+   {
+    fprintf(asm_out_file,"\n .global ");
+    fprintf(asm_out_file,"%s\n",XSTR(symref,0));
+   }
+}
+
+/* Following function calculates length for a function call it accepts rtx
+   operands and number as integer which distinguishes for which funtion to calculate length  */
+
+unsigned int
+compute_call_length(rtx *operands,int number)
+{
+
+enum machine_mode mode=GET_MODE(operands[number]);
+  if(TARGET_LARGE)
+    {
+     if(REG_P(operands[number]))
+     return 22;
+     else if (REG_P(XEXP(operands[number],0)))
+       {
+	    return 22;
+	   }
+	 else
+	   {
+	    if(strcmp((XSTR(XEXP(operands[number],0),0)),"__main")==0)
+      	return 0;
+      	else
+      	return 4;
+       }
+    }
+
+    else
+    {
+	if (GET_CODE(operands[number]) == MEM &&REG_P(XEXP(operands[number],0)))
+	    return 2;
+	else
+		return 4;
+	}
+}
+
+/* Following function returns the length of add and subtract instructions  */
+
+unsigned int
+compute_add_length(rtx *operands)
+{
+ enum machine_mode mode=GET_MODE(operands[0]);
+   if(TARGET_LARGE)
+    {
+	  switch(mode)
+	  {
+	    case QImode:
+	    case HImode:
+	      switch(which_alternative)
+	        {
+	        case 0: return 2;
+	        case 1: return 4;
+	        case 2:
+	        case 3:
+	        case 4: return 8;
+		    }
+        case SImode:
+          switch(which_alternative)
+            {
+            case 0:return 4;
+            case 1:return 8;
+            case 2:return 12;
+            case 3:return 12;
+            case 4:
+		    }
+      }
+	}
+   else
+    {
+
+	    switch(mode)
+	      {
+	        case QImode:
+	  	    case HImode:
+	  	      switch(which_alternative)
+	  	        {
+	  	        case 0: return 2;
+	  	        case 1:
+	  	        case 2:
+	  	        case 3:
+	  	        case 4:  return 4;
+			    }
+	          case SImode:
+	           switch(which_alternative)
+	            {
+	             case 0:return 4;
+	             case 1:
+	             case 2:
+	             case 3:return 8;
+	             case 4:
+			    }
+	      }
+
+	}
+}
+
+
+unsigned int
+compute_mov_length (rtx *operands)
+{
+ enum machine_mode mode = GET_MODE (operands[0]);
+ if(TARGET_LARGE)
+ {
+   switch(mode)
+    {
+	 case QImode:
+	   switch(which_alternative)
+	   {
+	   case 0:return 2;
+	   case 1:return 2;
+	   case 2:return 8;
+	   case 3:return 8;
+	   case 4:return 8;
+       }
+	 break;
+	 case HImode:
+	    switch(which_alternative)
+	   	   {
+	   	   case 0:return 2;
+	   	   case 1:return 2;
+	   	   case 2:return 8;
+
+	   	   case 3:
+	   	     if(GET_CODE(XEXP(operands[1],0))==SYMBOL_REF||GET_CODE(XEXP(operands[1],0))==CONST)
+	   	       return 8;
+	   	     else if (GET_CODE(XEXP(operands[1],0))!=PLUS&&REGNO(XEXP(operands[1],0))!=0)
+	   	       return 8;
+	   	     else
+	   	       return 4;
+
+	   	   case 4:
+	   	   if(GET_CODE(XEXP(operands[0],0))==SYMBOL_REF||GET_CODE(XEXP(operands[0],0))==CONST)
+		   	   	       return 8;
+		   	   	     else if (GET_CODE(XEXP(operands[0],0))!=PLUS&&REGNO(XEXP(operands[0],0))!=0)
+		   	   	       return 8;
+		   	   	     else
+	   	       return 4;
+       }
+	 break;
+	 case SImode:
+	 case SFmode:
+	     switch(which_alternative)
+			   {
+			   case 0:return 4;
+			   case 1:return 4;
+			   case 2:return 12;
+			   case 3:
+			   if(GET_CODE(XEXP(operands[1],0))==SYMBOL_REF||GET_CODE(XEXP(operands[1],0))==CONST)
+			   	   	       return 12;
+			   	   	     else if (GET_CODE(XEXP(operands[1],0))!=PLUS&&REGNO(XEXP(operands[1],0))!=0)
+			   	   	       return 12;
+			   	   	     else
+			   	   	       return 8;
+
+			   case 4:
+			   if(GET_CODE(XEXP(operands[0],0))==SYMBOL_REF||GET_CODE(XEXP(operands[0],0))==CONST)
+			   		   	   	       return 12;
+			   		   	   	     else if (GET_CODE(XEXP(operands[0],0))!=PLUS&&REGNO(XEXP(operands[0],0))!=0)
+			   		   	   	       return 12;
+			   		   	   	     else
+			   	   	       return 8;
+
+       }
+	 break;
+	}
+ }
+ else
+ {
+   switch(mode)
+       {
+   	 case QImode:
+   	   switch(which_alternative)
+   	   {
+   	   case 0:return 2;
+   	   case 1:return 2;
+   	   case 2:return 4;
+   	   case 3:return 4;
+   	   case 4:return 4;
+       }
+   	 break;
+   	 case HImode:
+   	    switch(which_alternative)
+   	   	   {
+   	   	   case 0:return 2;
+   	   	   case 1:return 2;
+   	   	   case 2:return 4;
+   	   	   case 3:return 4;
+   	   	   case 4:return 4;
+          }
+   	 break;
+   	 case SImode:
+   	 case SFmode:
+   	     switch(which_alternative)
+   			   {
+   			   case 0:return 4;
+   			   case 1:return 4;
+   			   case 2:return 8;
+   			   case 3:return 8;
+   			   case 4:return 8;
+          }
+   	 break;
+	}
+ }
+}
+
+/* If the next function argument with MODE and TYPE is to be passed in
+   a register, return a reg RTX for the hard register in which to pass
+   the argument.  CUM represents the state after the last argument.
+   If the argument is to be pushed, NULL_RTX is returned.  */
+
+rtx
+function_arg (int cum, enum machine_mode mode,
+	      tree type, int named)
+{
+
+
+  rtx result = NULL_RTX;
+  const char *fname;
+  int regpass = 5;
+
+  /* Never pass unnamed arguments in registers.  */
+  if (!named)
+    return NULL_RTX;
+
+
+
+
+  if (regpass)
+    {
+      int size;
+
+      if (mode == BLKmode)
+	size = int_size_in_bytes (type);
+      else
+	size = GET_MODE_SIZE (mode);
+
+      if (cum < (NREGS_FOR_REG_PARM*UNITS_PER_WORD-1)&&(size + cum) <= NREGS_FOR_REG_PARM * UNITS_PER_WORD)
+	result = gen_rtx_REG (mode, 8 + (cum) / UNITS_PER_WORD);
+    }
+
+  return result;
+}
+extern int target_flags;
+xc16x_file_start (void)
+{
+  default_file_start ();
+                                                                               
+  if (TARGET_LARGE)
+    fputs ("\t.xc16xl\n", asm_out_file);
+  else if (TARGET_SMALL)
+    fputs ("\t.xc16xs\n", asm_out_file);
+  else
+    fputs ("\t.xc16x\n", asm_out_file);
+}
+
+
+#undef  TARGET_ASM_FUNCTION_PROLOGUE
+#define TARGET_ASM_FUNCTION_PROLOGUE xc16x_output_function_prologue
+
+#undef  TARGET_ASM_FUNCTION_EPILOGUE
+#define TARGET_ASM_FUNCTION_EPILOGUE xc16x_output_function_epilogue
+
+#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
+#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
+#undef TARGET_ATTRIBUTE_TABLE
+#define TARGET_ATTRIBUTE_TABLE xc16x_attribute_table
+#undef TARGET_ASM_FILE_START
+#define TARGET_ASM_FILE_START xc16x_file_start
+#undef TARGET_DEFAULT_TARGET_FLAGS
+#define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
+
+#undef TARGET_INSERT_ATTRIBUTES
+#define TARGET_INSERT_ATTRIBUTES xc16x_insert_attributes
+#undef TARGET_ASM_ALIGNED_HI_OP
+#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
+
+#undef TARGET_ASM_EXTERNAL_LIBCALL
+#define TARGET_ASM_EXTERNAL_LIBCALL xc16x_ext_libcall
+struct gcc_target targetm = TARGET_INITIALIZER;
diff -Naur gcc-4.2-20060218orig/gcc/config/xc16x/xc16x.h gcc-4.2-20060218/gcc/config/xc16x/xc16x.h
--- gcc-4.2-20060218orig/gcc/config/xc16x/xc16x.h	1970-01-01 05:30:00.000000000 +0530
+++ gcc-4.2-20060218/gcc/config/xc16x/xc16x.h	2006-03-03 17:12:21.410076280 +0530
@@ -0,0 +1,846 @@
+/* Definitions of target machine for GNU compiler for the Infineon xc16x cpu.
+   Copyright (C)  2006
+   Free Software Foundation, Inc.
+
+   Contributed by Shrirang Khisti On behalf of KPIT Cummins Infosystems Ltd.
+   
+   This file is part of GCC.
+
+   GGC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 2, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING.  If not, write to
+   the Free Software Foundation, 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA */
+
+
+
+
+/*  Variable target_flags is used to distingusih between different target options specified
+   on the command line.  */
+#ifndef GCC_XC16X_H
+#define GCC_XC16X_H
+
+
+#define TARGET_VERSION fprintf (stderr, " (Infineon xc16x)");
+
+
+/* #define STARTFILE_SPEC "crt0.o%S" */
+/* Different target related switches supported are
+    -mtiny
+    -msmall
+    -mlarge
+    -mintrom
+    -mno-dppsave
+*/
+
+#define TARGET_DEFAULT (MASK_TINY) /* Default target is tiny  */
+
+/*/---------------------------------------------------------------------------------------------------*/
+
+/* Target machine storage layout  */
+
+/* Define this if most significant bit is lowest numbered
+   in instructions that operate on numbered bit-fields.  */
+
+
+
+#define BITS_BIG_ENDIAN  0
+
+/* Define this if most significant byte of a word is the lowest numbered.  */
+
+#define BYTES_BIG_ENDIAN  0
+
+/* Define this if most significant word of a multiword number is numbered.  */
+
+#define WORDS_BIG_ENDIAN 0
+
+/* Number of bits in an addressible storage unit  */
+ #define BITS_PER_UNIT 8
+
+/* Width in bits of a "word", which is the contents of a machine register.  */
+#define BITS_PER_WORD 16
+
+/* Width of a word, in units (bytes).  */
+#define UNITS_PER_WORD 2
+
+#define MIN_UNITS_PER_WORD 2
+
+
+
+/* Allocation boundary (in *bits*) for storing pointers in memory.  */
+#define POINTER_BOUNDARY (TARGET_LARGE ? 32 : 16)
+
+/* Boundary (in *bits*) on which stack pointer should be aligned.  */
+#define STACK_BOUNDARY 16
+
+/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
+#define PARM_BOUNDARY 16
+
+/* Allocation boundary (in *bits*) for the code of a function.  */
+#define FUNCTION_BOUNDARY 16
+
+/* Alignment of field after `int : 0' in a structure.  */
+#define EMPTY_FIELD_BOUNDARY 16
+
+/* Every structure's size must be a multiple of this.  */
+ #define STRUCTURE_SIZE_BOUNDARY 16
+
+/* A bitfield declared as `int' forces `int' alignment for the struct.  */
+#define PCC_BITFIELD_TYPE_MATTERS 1
+
+/* No data type wants to be aligned rounder than this.  */
+#define BIGGEST_ALIGNMENT 16
+
+/* Define this if move instructions will actually fail to work
+   when given unaligned data.  */
+#define STRICT_ALIGNMENT  1
+
+#define MAX_FIXED_MODE_SIZE	32
+
+/* ------------------------------------------------------------------------------------------------------ */
+/* Standard register usage.  */
+
+/* Number of actual hardware registers.
+   The hardware registers are assigned numbers for the compiler
+   from 0 to just below FIRST_PSEUDO_REGISTER.
+   All registers that the compiler knows about must be given numbers,
+   even those that are not normally considered general registers.  */
+#define FIRST_PSEUDO_REGISTER 16
+
+#define FIXED_REGISTERS \
+ /* r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15*/  \
+    {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,  0,  0,  0,  0, 0}
+
+/* 1 for registers not available across function calls.
+   These must include the FIXED_REGISTERS and also any
+   registers that can be used without being saved.
+   The latter must include the registers where values are returned
+   and the register where structure-value addresses are passed.
+   Aside from that, you can include as many other registers as you like.  */
+
+#define CALL_USED_REGISTERS \
+ /* r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15 */  \
+     {1,1,0,0,1,1,1,1,1,1,1,1,1,0,0,0}
+
+#define REG_ALLOC_ORDER \
+     {2,3,4, 5, 6, 7, 8, 9, 10, 11, 12,13,14, 15, 0, 1 }
+
+/* ------------------------------------------------------------------------------------------------------ */
+/* This section is all about how values fit in the registers
+  Return number of consecutive hard regs needed starting at reg REGNO
+   to hold something of mode MODE.
+
+   This is ordinarily the length in words of a value of mode MODE
+   but can be less for certain modes in special long registers.  */
+
+#define HARD_REGNO_NREGS(REGNO, MODE)   \
+   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
+
+/* Here 1 implies that it is permissible to store value of mode mode in
+   in hard reg or starting from that  hard reg no  */
+
+
+  #define HARD_REGNO_MODE_OK(REGNO, MODE) \
+  (((MODE)== QImode && REGNO < 8) ||((MODE) > QImode ))
+
+/* Currently  this macro is returning 0 but it can be further modified  */
+
+#define MODES_TIEABLE_P(MODE1, MODE2) 0
+
+
+/* ------------------------------------------------------------------------------------------------------- */
+
+/* Register to use for pushing function arguments.  */
+#define STACK_POINTER_REGNUM 0
+
+/* Base register for access to local variables of the function.  */
+#define FRAME_POINTER_REGNUM 1
+
+/* Value should be nonzero if functions must have frame pointers.
+   Zero means the frame pointer need not be set up (and parms
+   may be accessed via the stack pointer) in functions that seem suitable.
+   This is computed in `reload', in reload1.c.  */
+#define FRAME_POINTER_REQUIRED 0
+
+/* Base register for access to arguments of the function.  */
+#define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
+
+/* Register in which static-chain is passed to a function.
+   */
+
+#define STATIC_CHAIN_REGNUM 12
+
+
+ /* #define STRUCT_VALUE_REGNUM 11 */
+
+
+/* ---------------------------------------------------------------------------------------------------- */
+/* Define the classes of registers for register constraints in the
+   machine description.  Also define ranges of constants.
+
+   One of the classes must always be named ALL_REGS and include all hard regs.
+   If there is more than one class, another class must be named NO_REGS
+   and contain no registers.
+
+   The name GENERAL_REGS must be the name of a class (or an alias for
+   another name such as ALL_REGS).  This is the class of registers
+   that is allowed by "g" or "r" in a register constraint.
+   Also, registers outside this class are allocated only when
+   instructions express preferences for them.
+
+   The classes must be numbered in nondecreasing order; that is,
+   a larger-numbered class must never be contained completely
+   in a smaller-numbered class.
+
+   For any two classes, it is very desirable that there be another
+   class that represents their union.  */
+
+enum reg_class \
+    { NO_REGS,  BYTE_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES };
+
+#define N_REG_CLASSES (int) LIM_REG_CLASSES
+
+/* Give names of register classes as strings for dump file.   */
+
+#define REG_CLASS_NAMES \
+ {"NO_REGS", "BYTE_REGS","GENERAL_REGS", "ALL_REGS" };
+
+#define REG_CLASS_CONTENTS \
+ {                                          \
+  0x00000000,     /* NO_REGS    */          \
+  0x000000ff,     /* BYTE_REGS  */          \
+  0x0000ffff,     /* GENERAL_REGS */        \
+  0x0000ffff      /* ALL_REGS   */          \
+ }
+
+
+ /* The same information, inverted:
+    Return the class number of the smallest class containing
+    reg number REGNO.  This could be a conditional expression
+    or could index an array.  */
+
+
+#define REGNO_REG_CLASS(REGNO) \
+  ((REGNO) < 8 ? BYTE_REGS : GENERAL_REGS)
+
+/* The class value for index registers, and the one for base regs.  */
+
+#define INDEX_REG_CLASS  GENERAL_REGS
+
+#define BASE_REG_CLASS   GENERAL_REGS
+
+/* Get reg_class from a letter such as appears in the machine description.  */
+
+#define REG_CLASS_FROM_LETTER(C) \
+ (((C) == 'b' || (C) == 'B' ) ? BYTE_REGS :NO_REGS)
+
+/* When defined, the compiler allows registers explicitly used in the
+   rtl to be used as spill registers but prevents the compiler from
+   extending the lifetime of these registers.  */
+
+#define SMALL_REGISTER_CLASSES 1
+
+/* Return the maximum number of consecutive registers
+   needed to represent mode MODE in a register of class CLASS.  */
+
+#define CLASS_MAX_NREGS(CLASS, MODE)	\
+  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
+
+ #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)	\
+    ((C) == 'G' ? (VALUE) == CONST0_RTX (SFmode)	\
+     : 0)
+/* Macros to check register numbers against specific register classes.  */
+
+
+#define REGNO_OK_FOR_INDEX_P(regno) 0
+
+/*Expression to indicate that register is used for base or not  */
+#define REGNO_OK_FOR_BASE_P(regno) \
+((regno) < FIRST_PSEUDO_REGISTER \
+    || (reg_renumber[regno] < FIRST_PSEUDO_REGISTER  && reg_renumber[regno] >= 0))
+
+
+
+/* Given an rtx X being reloaded into a reg required to be
+   in class CLASS, return the class of reg to actually use.
+   In general this is just CLASS; but on some machines
+   in some cases it is preferable to use a more restrictive class. */
+
+#define PREFERRED_RELOAD_CLASS(X,CLASS)  \
+  (GET_MODE (X) == QImode ? \
+     BYTE_REGS : CLASS )
+
+#define PREFERRED_OUTPUT_RELOAD_CLASS PREFERRED_RELOAD_CLASS
+/* ----------------------------------------------------------------------------------------------- */
+/* Stack layout; function entry, exit and calling.  */
+
+/*   Define this if pushing a word on the stack
+     makes the stack pointer a smaller address.  */
+#define STACK_GROWS_DOWNWARD
+
+/* Define this if the nominal address of the stack frame
+   is at the high-address end of the local variables;
+   that is, each additional local variable allocated
+   goes at a more negative offset in the frame.  */
+
+#define FRAME_GROWS_DOWNWARD 1
+
+
+#define PUSH_ROUNDING(BYTES) (((BYTES) +1) & ~1)
+
+#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
+
+
+/* Offset of first parameter from the argument pointer register value.  */
+/* Is equal to the size of the saved fp + pc, even if an fp isn't
+   saved since the value is used before we know.  */
+
+#define FIRST_PARM_OFFSET(FNDECL) \
+ (flag_omit_frame_pointer ? 0:2)
+
+
+#define STARTING_FRAME_OFFSET 0
+/* Define how to find the value returned by a function.
+   VALTYPE is the data type of the value (as a tree).
+   If the precise function being called is known, FUNC is its FUNCTION_DECL;
+   otherwise, FUNC is 0.  */
+
+/* On the xc16x the return value is in R4 regardless.  */
+#define RET_VAL_REG    4
+
+/* Define how to find the value returned by a function.
+   VALTYPE is the data type of the value (as a tree).
+   If the precise function being called is known, FUNC is its FUNCTION_DECL;
+   otherwise, FUNC is 0.
+
+   On the xc16x the return value is in R4/R5.  */
+
+#define FUNCTION_VALUE(VALTYPE, FUNC) \
+  gen_rtx_REG (TYPE_MODE (VALTYPE), RET_VAL_REG)
+
+/* Define how to find the value returned by a library function
+   assuming the value has mode MODE.  */
+
+/* On the xc16x the return value is in R4/R5.  */
+
+#define LIBCALL_VALUE(MODE) \
+  gen_rtx_REG (MODE, RET_VAL_REG)
+
+
+/* 1 if N is a possible register number for a function value.
+     On the C166, R4 is the only register thus used.  */
+
+#define FUNCTION_VALUE_REGNO_P(N) ((N) == RET_VAL_REG)
+
+
+
+#define NREGS_FOR_REG_PARM   5  /* Total no of registers for parameter passing  */
+#define FIRST_PARM_REG       8  /* First register used for parameter passing  */
+
+
+
+/* #define FUNCTION_ARG(CUM,MODE,TYPE,NAMED) \
+ (!NAMED ? 0 :	\
+	 ((CUM) < (NREGS_FOR_REG_PARM*UNITS_PER_WORD-1)	\
+	       &&  ((CUM)+ ((MODE) != BLKmode ?			\
+		      GET_MODE_SIZE(MODE):int_size_in_bytes (TYPE))	\
+		   <= (NREGS_FOR_REG_PARM*UNITS_PER_WORD))		\
+               ?  gen_rtx_REG((MODE), FIRST_PARM_REG+(CUM)/UNITS_PER_WORD) : 0)) */
+
+#define FUNCTION_ARG(CUM,MODE,TYPE,NAMED)  function_arg (CUM, MODE, TYPE, NAMED)
+#define FUNCTION_ARG_REGNO_P(N) ((N) >= FIRST_PARM_REG \
+                           && (N) <= FIRST_PARM_REG+NREGS_FOR_REG_PARM)
+
+
+
+
+
+/*---------------------------------------------------------------------------------------
+ Following macros are regarding cumulative arguments and its initialization */
+
+
+
+#define CUMULATIVE_ARGS int
+
+/* Initialize a variable CUM of type CUMULATIVE_ARGS
+   for a call to a function whose data type is FNTYPE.
+   For a library call, FNTYPE is 0.
+   .  */
+
+#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME, INDIRECT, N_NAMED_ARGS)	\
+ ((CUM) = 0)
+
+
+/* Update the data in CUM to advance over an argument
+   of mode MODE and data type TYPE.
+   (TYPE is null for libcalls where that information may not be available.)
+   Here if odd bytes are passed as function argument then it is rounded to next higher
+   even number and added to value of cum  */
+
+#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
+ ((CUM) += ((MODE) != BLKmode				\
+	    ? (GET_MODE_SIZE (MODE) + 1) & ~1		\
+	    : (int_size_in_bytes (TYPE) + 1) & ~1))
+
+   /* Output assembler code to FILE to increment profiler label # LABELNO
+   for profiling a function entry.  */
+
+#define FUNCTION_PROFILER(FILE, LABELNO)
+
+
+/* --------------------------------------------------------------------------------------- */
+
+/* This part of file have macros related to trampoline  */
+ /*
+      Ttrampoline code will be
+
+      0xfce6 : opcode for mov r12,#xxxx  Here r12 is static chain register number
+      0x00ea : opcode for jmpa cc_UC,fun jump to the function
+      This implementation is yet not perfect for Large Memory model
+     */
+
+
+
+#define TRAMPOLINE_SIZE  8
+#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
+do									    \
+    {									    \
+	                                           \
+	 rtx temp=gen_rtx_CONST_INT(HImode,-794);								    \
+	  emit_move_insn (gen_rtx_MEM (HImode, (TRAMP)), temp); \
+	  emit_move_insn (gen_rtx_MEM (Pmode, plus_constant ((TRAMP), 2)),  \
+			  (CXT));					    \
+	  emit_move_insn (gen_rtx_MEM (Pmode, plus_constant ((TRAMP), 4)),  \
+			  GEN_INT (0x00ea));				    \
+	  emit_move_insn (gen_rtx_MEM (Pmode, plus_constant ((TRAMP), 6)),  \
+			  (FNADDR));					    \
+									    \
+											\
+    }									    \
+  while (0)
+/* ---------------------------------------------------------------------------------------- */
+
+/* Definitions for register eliminations.
+
+   This is an array of structures.  Each structure initializes one pair
+   of eliminable registers.  The "from" register number is given first,
+   followed by "to".  Eliminations of the same "from" register are listed
+   in order of preference.
+
+   We have three registers that can be eliminated on the xc16x.
+   First, the frame pointer register can often be eliminated in favor
+   of the stack pointer register.  Secondly, the argument pointer
+   register  */
+
+#if 0
+#define ELIMINABLE_REGS				\
+{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},	\
+ { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},   \
+ { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
+
+/* Given FROM and TO register numbers, say whether this elimination is allowed.
+   Frame pointer elimination is automatically handled.
+   We would like to
+   convert ap into sp, not fp.
+   All other eliminations are valid.  */
+
+#define CAN_ELIMINATE(FROM, TO)					\
+ ( (TO) == STACK_POINTER_REGNUM	\
+  ? ! frame_pointer_needed					\
+  : 1)
+
+/* Here diff is total frame size + total no of reg saved*2  */
+#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)			\
+{									\
+						\
+      int regno;							\
+      int offset = 0;							\
+      for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)		\
+	if ((regs_ever_live[regno] && ! call_used_regs[regno]))		\
+	  offset += 2;							\
+									\
+      (OFFSET) = offset + get_frame_size () ;			\
+									\
+    }
+
+#endif
+#define INITIAL_FRAME_POINTER_OFFSET(DEPTH)			\
+{ int regno;							\
+  int offset = 0  ;     \
+  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)	\
+    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
+      offset += 2;						\
+  (DEPTH) = (offset + get_frame_size () ) ;			\
+}
+
+
+/* ------------------------------------------------------------------------------------------------- */
+
+/* Following part contains macros related to addressing modes and address checking */
+
+
+/* Addressing modes,  */
+
+#define HAVE_POST_INCREMENT 1
+
+#define HAVE_PRE_DECREMENT 1
+
+#define HAVE_PRE_MODIFY_REG  0
+#define HAVE_PRE_MODIFY_DISP  0
+/* Maximum number of registers that can appear in a valid memory address.  */
+
+#define MAX_REGS_PER_ADDRESS 1
+
+/* 1 if X is an rtx for a constant that is a valid address.  */
+/*  for the C166 allow only offsettables with positiv offset  */
+
+#define CONSTANT_ADDRESS_P(X)   \
+ ( GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
+   || GET_CODE (X) == CONST_DOUBLE					\
+   || GET_CODE (X) == CONST_INT						\
+   || (GET_CODE(X) == CONST &&  GET_CODE (XEXP ((X),0)) == PLUS 	\
+          && GET_CODE (XEXP (XEXP ((X),0), 0)) == SYMBOL_REF 		\
+          && GET_CODE (XEXP (XEXP ((X),0), 1)) == CONST_INT		\
+          && (INTVAL (XEXP (XEXP ((X),0),1)) >= 0 			\
+             ||  INTVAL (XEXP (XEXP ((X),0),1)) <= 32768) ))
+
+/* Following section checks validity of register X as an index register and base register  */
+
+#ifndef REG_OK_STRICT
+
+/* Nonzero if X is a hard reg that can be used as an index
+   or if it is a pseudo reg.  */
+
+#define REG_OK_FOR_INDEX_P(X) 1
+
+
+/* Nonzero if X is a hard reg that can be used as a base reg
+   or if it is a pseudo reg.   */
+
+#define REG_OK_FOR_BASE_P(X)   1
+
+
+#else
+
+/* Nonzero if X is a hard reg that can be used as an index.  */
+#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P(REGNO(X))
+
+/* Nonzero if X is a hard reg that can be used as a base reg.  */
+#define REG_OK_FOR_BASE_P(X)  REGNO_OK_FOR_BASE_P (REGNO (X))
+
+#endif
+
+
+
+/*
+   It isalways safe for this macro to do nothing.  It exists to recognize
+   opportunities to optimize the output.  */
+
+
+
+#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {}
+
+/* Go to LABEL if ADDR (a legitimate address expression)
+   has an effect that depends on the machine mode it is used for.
+   On the VAX, the predecrement and postincrement address depend thus
+   (the amount of decrement or increment being the length of the operand)  */
+
+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)	\
+ { if (GET_CODE (ADDR) == PRE_DEC) 	\
+     goto LABEL; }
+
+
+
+
+ #define RTX_OK_FOR_BASE_P(X)				\
+   ((REG_P (X) && REG_OK_FOR_BASE_P (X))			\
+    || (GET_CODE (X) == SUBREG && REG_P (SUBREG_REG (X))	\
+        && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
+
+ #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)		\
+   if (RTX_OK_FOR_BASE_P (X)) goto ADDR;			\
+   if (CONSTANT_ADDRESS_P (X)) goto ADDR;		\
+   if (GET_CODE (X) == PLUS				\
+       && GET_CODE (XEXP (X, 1))==CONST_INT		\
+      && RTX_OK_FOR_BASE_P (XEXP (X, 0))) goto ADDR;
+
+ /* ------------------------------------------------------------------------------------------- */
+ /* Specify the machine mode that this machine uses
+    for the index in the tablejump instruction.  */
+ #define CASE_VECTOR_MODE Pmode
+
+/* #define CASE_VECTOR_PC_RELATIVE 1  */
+  /* Specify the tree operation to be used to convert reals to integers.
+ #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR  */
+
+ /* This is the kind of divide that is easiest to do in the general case.
+ #define EASY_DIV_EXPR TRUNC_DIV_EXPR  */
+
+ /* Define this as 1 if `char' should by default be signed; else as 0.  */
+ #define DEFAULT_SIGNED_CHAR 0
+
+ /* Max number of bytes we can move from memory to memory
+    in one reasonably fast instruction.  */
+#define MOVE_MAX 2
+
+/* Following section describes macros related to  c data type size supported on xc16x  */
+
+#define SHORT_TYPE_SIZE  16
+#define INT_TYPE_SIZE    16
+#define LONG_TYPE_SIZE   32
+#define FLOAT_TYPE_SIZE  32
+#define DOUBLE_TYPE_SIZE 32
+#define LONG_LONG_TYPE_SIZE 64
+#define MOVE_RATIO  (TARGET_LARGE ? 12 : 6)
+
+
+#define SIZE_TYPE (TARGET_LARGE ? "long unsigned int" : "unsigned int")
+
+#define Pmode   \
+  (TARGET_LARGE ? PSImode : HImode)
+
+#define POINTER_SIZE							\
+  (TARGET_LARGE ? 32 : 16)
+
+#define PTRDIFF_TYPE						\
+  (TARGET_LARGE ? "long int" : "int")
+
+/* This flag, if defined, says the same insns that convert to a signed fixnum
+   also convert validly to an unsigned one.  */
+#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
+
+/* Nonzero if access to memory by bytes is slow and undesirable.  */
+#define SLOW_BYTE_ACCESS 0
+
+
+/* A function address in a call instruction
+   is a word address (for indexing purposes)
+   so give the MEM rtx a word mode.  */
+
+#define FUNCTION_MODE HImode
+
+
+/* Check a `double' value for validity for a particular machine mode.  */
+
+
+#define CHECK_FLOAT_VALUE(mode, d, overflow) \
+  if ((mode) == SFmode) \
+    { \
+      if ((d) > 1.701411733192643e+38) \
+	{ error ("magnitude of constant too large for `float'"); \
+	  (d) = 1.701411733192643e+38; } \
+      else if ((d) < -1.701411733192643e+38) \
+	{ error ("magnitude of constant too large for `float'"); \
+	  (d) = -1.701411733192643e+38; } \
+      else if (((d) > 0) && ((d) < 2.9387358770557188e-39)) \
+	{ warning ("`float' constant truncated to zero"); \
+	  (d) = 0.0; } \
+      else if (((d) < 0) && ((d) > -2.9387358770557188e-39)) \
+	{ warning ("`float' constant truncated to zero"); \
+	  (d) = 0.0; } \
+    }
+
+
+/* ------------------------------------------------------------------------------------------------- */
+/* Following part of the file contains macros related to assembler output formatting. */
+
+/* Control the assembler format that we output.  */
+
+/* Output to assembler file text saying following lines
+   may contain character constants, extra white space, comments, etc.  */
+
+#define ASM_APP_ON "#APP\n"
+
+/* Output to assembler file text saying following lines
+   no longer contain unusual constructs.  */
+
+#define ASM_APP_OFF "#NO_APP\n"
+
+#define FILE_ASM_OP "\t.file\n"
+
+/* Write the sections names  */
+#define TEXT_SECTION_ASM_OP "\t.section .text"
+#define DATA_SECTION_ASM_OP "\t.section .data"
+#define BSS_SECTION_ASM_OP "\t.section .bss"
+#define READONLY_DATA_SECTION_ASM_OP "\n\t.section .rodata\n"
+/* #define READONLY_DATA_SECTION() READONLY_DATA_SECTION_ASM_OP  */
+
+/* How to put comment in assembly code  */
+#define ASM_COMMENT_START  ";"
+
+#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
+  sprintf (LABEL, "*.%s%d", PREFIX, (unsigned)(NUM))
+
+#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
+  fprintf (FILE, "%s.L%d\n", ASM_WORD_OP, VALUE)
+
+/* This is how to output an element of a case-vector that is relative.  */
+
+/*#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
+  fprintf (FILE, "%s.L%d-.L%d\n", ASM_WORD_OP, VALUE, REL)*/
+
+/* This is how to output an insn to push a register on the stack.
+   It need not be very fast code.  */
+
+#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
+  fprintf (FILE, "\tmov [-r%d],%s\n", STACK_POINTER_REGNUM, reg_names[REGNO])
+
+/* This is how to output an insn to pop a register from the stack.
+   It need not be very fast code.  */
+
+#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
+  fprintf (FILE, "\tmov %s,[r%d+]\n", reg_names[REGNO], STACK_POINTER_REGNUM)
+
+/* This is how to output an assembler line
+   that says to advance the location counter
+   to a multiple of 2*LOG bytes.  */
+
+#define ASM_OUTPUT_ALIGN(FILE, LOG)		\
+  if ((LOG) != 0)				\
+    fprintf (FILE, "\t.align %d\n", (LOG))
+
+#define ASM_OUTPUT_SKIP(FILE, SIZE) \
+  fprintf (FILE, "\t.space %d\n", (int)(SIZE))
+
+/* This says how to output an assembler line
+   to define a global common symbol.  */
+
+#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)	\
+( fputs ("\t.comm ", (FILE)),				\
+  assemble_name ((FILE), (NAME)),			\
+  fprintf ((FILE), ",%lu\n", (unsigned long)(SIZE)))
+
+/* This says how to output a n assembler line
+    to define a local symbol  */
+
+#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)	\
+( fputs ("\t.lcomm ", (FILE)),				\
+  assemble_name ((FILE), (NAME)),			\
+  fprintf ((FILE), ",%d\n", (int)(SIZE)))
+
+/* Following macro will call function "print_operand" in xc16x.c file which takes
+   total responsibility of printing particular operand  */
+
+#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
+
+/* Print a memory operand whose address is X, on file FILE.
+   This uses a function in xc16x.c.  */
+
+#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
+
+/* The prefix to add to user-visible assembler symbols.  */
+
+#define USER_LABEL_PREFIX "_"
+
+/* Globalizing directive for a label.  */
+#define GLOBAL_ASM_OP "\t.global "
+
+/* The assembler op to get a word, 2 bytes for the H8/300, 4 for H8/300H.  */
+#define ASM_WORD_OP "\t.word\t"
+
+/* This macro is to generate function name  */
+
+#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
+   ASM_OUTPUT_LABEL (FILE, NAME)
+
+#define REGISTER_NAMES \
+ {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" }
+
+#define REGISTER_TARGET_PRAGMAS() \
+ do                \
+  {					\
+	  c_register_pragma (0, "disable_intr", xc16x_disable_intr);	\
+      c_register_pragma (0, "interrupt_handler", xc16x_interrupt_handler);	\
+      c_register_pragma (0, "interrupt_noreturn", xc16x_interrupt_noreturn);	\
+  } \
+   while(0)
+
+#define NOTICE_UPDATE_CC(EXP, INSN) {CC_STATUS_INIT;}
+
+#define CC_STATUS_INIT
+
+    /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
+	   is done just by pretending it is already truncated.  */
+
+#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 0
+
+#define TARGET_CPU_CPP_BUILTINS()			\
+  do							\
+    { \
+    if(TARGET_LARGE)\
+    {\
+    builtin_define ("__xc16xL__");			\
+		  builtin_assert ("cpu=xc16x");			\
+		  builtin_assert ("machine=xc16x");		\
+    }\
+    else if(TARGET_SMALL) \
+    { \
+	builtin_define ("__xc16xS__");			\
+			  builtin_assert ("cpu=xc16x");			\
+			  builtin_assert ("machine=xc16x");		\
+    }\
+    else\
+    {\
+	builtin_define ("__xc16x__");			\
+			  builtin_assert ("cpu=xc16x");			\
+			  builtin_assert ("machine=xc16x");		\
+	}\
+	}						\
+	while(0)
+
+
+/* Nonzero if the constant value X is a legitimate general operand.
+   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
+
+#define LEGITIMATE_CONSTANT_P(X) (1)
+#define CONST_OK_FOR_LETTER_P(value,c) 0
+
+#define ASM_OUTPUT_LABELREF(FILE,NAME)	\
+  fprintf (FILE, "_%s", NAME)
+
+#define  POINTERS_EXTEND_UNSIGNED 1
+
+
+#define LINK_SPEC "%{mlarge: -m elf32xc16xl} %{msmall: -m elf32xc16xs}"
+#define EXTRA_CONSTRAINT(OP, C)			\
+  (   (C) == 'S' ? OK_FOR_S (OP) :			\
+      (C) == 'R' ? OK_FOR_R (OP) :	\
+      (C) == 'T' ? OK_FOR_R (OP) :	\
+        0)
+
+#define OK_FOR_S(op) \
+ (GET_CODE (op) == MEM && ((GET_CODE (XEXP (op, 0))==SYMBOL_REF)||(GET_CODE(XEXP(op,0)))==CONST	)		\
+    ? 1 \
+    : 0)
+
+#define OK_FOR_T(op) \
+  (GET_CODE(op)==MEM && (GET_CODE (XEXP (op, 0))==PLUS))\
+     ? 0 \
+     : 1)
+
+#define OK_FOR_R(op) \
+  (GET_CODE (op)==MEM &&(GET_CODE(XEXP(op,0))==REG||GET_CODE(XEXP(op,0))==SYMBOL_REF) \
+  ? 1 \
+  :0)
+
+#define OBJECT_FORMAT_ELF 1
+#define DBX_DEBUGGING_INFO
+
+/*  For DWARF2 debugging information */
+
+#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
+#define TARGET_ASM_NAMED_SECTION  default_elf_asm_named_section
+#define DWARF2_DEBUGGING_INFO 1
+#define DWARF2_ASM_LINE_DEBUG_INFO 1
+
+#endif
diff -Naur gcc-4.2-20060218orig/gcc/config/xc16x/xc16x.md gcc-4.2-20060218/gcc/config/xc16x/xc16x.md
--- gcc-4.2-20060218orig/gcc/config/xc16x/xc16x.md	1970-01-01 05:30:00.000000000 +0530
+++ gcc-4.2-20060218/gcc/config/xc16x/xc16x.md	2006-03-03 17:14:37.969316120 +0530
@@ -0,0 +1,2362 @@
+;; GCC machine description for Infineon xc16x
+;; Copyright (C)  2006 Free Software Foundation, Inc.
+
+;; Contributed by Shrirang Khisti on behalf of KPIT Cummins Infosystems Ltd.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+
+;; This is a machine description file for target xc16x Infineon chip.
+;; File contains basically define_insn and define_expand patterns for rtx generation and code   
+;; generation.
+
+
+
+
+;; Print operand must support
+;; X - For outputting 8 byte register operand
+;; f - For generating regopno+1 reg specially for 32 bit operation
+;; l - For printing Label directly specially in jump instructions.
+;; c,d,C,D,Y : Specially used for large memory model
+
+;; PSI :- Partial single integer : It is specially taken as a mode for pointers for large target
+;; memory model. It is useful to distinguish pointer operations by adding PSI mode
+
+
+
+
+;; Set the attribute "type"  for the instructions
+;; Right now only two types are defined arithmatic and branch.
+;; Default type for any instruction will be arith
+(include "predicates.md")
+(define_attr "type" "branch,arith"
+	     (const_string "arith"))
+
+
+;; Set attribute length for the instructions
+;; Here for branch instructions according to target jump its size is decided
+
+
+(define_attr "length" "" 
+ (cond [(eq_attr "type" "branch")
+ (if_then_else (and (ge (minus (match_dup 0) (pc))
+ 			(const_int -80))
+               	    (le (minus (match_dup 0) (pc))
+ 			(const_int 80)))
+ (const_int 2) (const_int 4))]
+         
+(const_int 2)))
+
+
+(define_insn "*large_premodify123"
+[(set (mem :QI(pre_modify:PSI 
+              (match_operand:PSI 0 "register_operand" "r")
+              (plus: PSI (match_operand:PSI 1 "register_operand" "0")
+                         (match_operand:PSI 2 "immediate_operand" "i"))))
+                         (match_operand:QI 3 "general_operand" "g"))]                
+""
+"*
+{
+ output_asm_insn(\"add %T0,%2\",operands);
+ output_asm_insn(\"mov [-r0],%f0\",operands);
+ output_asm_insn(\"mov %f0,%3\",operands);
+ output_asm_insn(\"mov [%T0],%f0\",operands);
+ return \"mov %f0,[r0+]\";
+}
+"
+[(set_attr "length" "16")])
+
+
+(define_insn "*premodify"
+[(set (mem :QI(pre_modify:HI 
+              (match_operand:HI 0 "register_operand" "r")
+              (plus: HI (match_operand:HI 1 "register_operand" "0")
+                        (match_operand:HI 2 "immediate_operand" "i"))))
+                        (match_operand:QI 3 "general_operand" "g"))]                
+""
+"*
+{
+ output_asm_insn(\"add %T0,%2\",operands);
+ output_asm_insn(\"mov [-r0],%f0\",operands);
+ output_asm_insn(\"mov %f0,%3\",operands);
+ output_asm_insn(\"mov [%T0],%f0\",operands);
+ return \"mov %f0,[r0+]\";
+
+}"
+[(set_attr "length" "16")])
+
+(define_expand "insv"
+  [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "")
+			 (match_operand:HI 1 "immediate_operand" "")
+			 (match_operand:HI 2 "general_operand" ""))
+                  	 (match_operand:HI 3 "register_operand" ""))]
+	
+  ""
+  "if(INTVAL(operands[1])!=1)
+   FAIL;
+  "
+    )
+    
+    
+(define_insn "*insv_si_1_n"
+  [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
+        (const_int 1)
+	(match_operand:HI 1 "immediate_operand" "n"))
+	(match_operand:HI 2 "register_operand" "r"))]
+			 
+	 ""
+	 "bmov %0.%s1,%2.0"
+[(set_attr "length" "4")])
+
+;;QI mode move instruction
+
+(define_expand "movqi"
+   	   [(set (match_operand:QI 0 "general_operand_dst" "")
+		(match_operand:QI 1 "general_operand_src" ""))]
+		""
+		"
+		"
+)
+
+
+
+(define_insn "*movqi"
+   [(set (match_operand:QI 0 "general_operand_dst" "=r,<,b,b,m")
+         (match_operand:QI 1 "general_operand_src" "r>,b,i,m,b"))]
+	""
+	"*
+	{
+	 switch(which_alternative)
+	 {
+	   
+	  case 4: 
+	      		    
+	  if(GET_CODE(XEXP(operands[0],0))==CONST_INT)
+	  {
+	         rtx p_no[2];
+	         rtx xop[2];                                                                                 
+	         xop[1]=operands[1];
+	         xop[0]=XEXP(operands[0],0);
+	         if(TARGET_LARGE)
+	   	 {
+	     	   if(INTVAL(XEXP(operands[0],0))>0xffff)
+	     	   {
+	     	 	 p_no[0]=gen_rtx_CONST_INT(HImode,INTVAL(XEXP(operands[0],0))/0x4000);
+	     		      		
+	     		 xop[0]=gen_rtx_CONST_INT(HImode,INTVAL(XEXP(operands[0],0))%0x4000);
+	     		      		
+	     		 output_asm_insn(\"extp %0,#0x1\",p_no);
+	     		 output_asm_insn(\"movb %i0,%X1\",xop);
+	     		      		
+	     		 return \"\";
+	           }	     		      		
+	     	 }
+   	       
+  	         output_asm_insn(\"movb %i0,%X1\",xop); 		     
+                             		       	
+                 return \"\";
+	  }
+		      		
+ 	  if(TARGET_LARGE)
+	  {
+		    		    
+	  	if(GET_CODE(XEXP(operands[0],0))==SYMBOL_REF||GET_CODE(XEXP(operands[0],0))==CONST)
+	        {
+	   	        output_asm_insn(\"extp #pag: %X0,#0x1\",operands);
+		        return \"movb pof:%X0,%X1\";
+	        }
+	        else
+	   	{
+		        if(GET_CODE(XEXP(operands[0],0))!=PLUS&&REGNO(XEXP(operands[0],0))!=0)
+		        {
+				      		   
+		             output_asm_insn(\"extp %d0,#0x1\",operands);
+		        }
+				   
+		             return \"movb	%X0,%X1\"; 
+                }
+ 		                  
+  	  }
+	      		   return \"movb	%X0,%X1\"; 
+
+	 case 3:
+    
+	       if(GET_CODE(XEXP(operands[1],0))==CONST_INT)
+	       {
+	       	      rtx xop[2];
+		      rtx p_no[2];
+		      xop[0]=operands[0];
+		      xop[1]=XEXP(operands[1],0);
+					
+		      if(TARGET_LARGE)
+	     	      {
+	     	    	  if(INTVAL(XEXP(operands[1],0))>0xffff)
+	     		  {
+	     		     p_no[0]=gen_rtx_CONST_INT(HImode,INTVAL(XEXP(operands[1],0))/0x4000);
+	     		     xop[1]=gen_rtx_CONST_INT(HImode,INTVAL(XEXP(operands[1],0))%0x4000);
+	     		     output_asm_insn(\"extp %0,#0x1\",p_no);
+	     		     output_asm_insn(\"movb %X0,%i1\",operands);
+	     		     return \"\";
+	                  }	     		      		
+	     	       }				     	    
+				           
+		       output_asm_insn(\"movb %X0,%i1\",xop);
+		       return \"\";
+	      }
+	                        
+	      if(TARGET_LARGE)
+	      {    	      		     
+	    	     if(GET_CODE(XEXP(operands[1],0))==SYMBOL_REF||GET_CODE(XEXP(operands[1],0))==CONST)
+		     {
+		      		   
+		        output_asm_insn(\"extp #pag: %X1,#0x1\",operands);
+				   
+		        return \"movb %X0, pof:%X1\";
+		        return \"\";
+		     }
+		     else
+		     {
+		        if(GET_CODE(XEXP(operands[1],0))!=PLUS&&REGNO(XEXP(operands[1],0))!=0)
+		        {
+				         
+		           output_asm_insn(\"extp  %d1,#0x1\",operands);
+				         
+		        }
+		        return \"movb	%X0,%X1\"; 
+				   		    		                     
+ 		    }
+		      		         		   
+		      		   
+	      }
+	      else
+	  	     return \"movb	 %X0,%X1\";
+		      		  
+	 case 2:
+	  	     return \"movb %X0,%X1\";
+		      		      
+ 	 case 0:
+ 	            if(TARGET_LARGE)
+	            {
+		      if(GET_CODE(operands[1])!=REG)
+        	      {
+			  if(REGNO(XEXP(operands[1],0))>1)
+			  output_asm_insn(\"extp %f1,#0x1\",XEXP(operands[1],0));
+                          if(REGNO(operands[0])<8)
+                             return \"movb %X0,%T1\";
+		 	  else
+			     return \"mov %T0,%T1\";	
+		      }
+		      return \"mov %T0,%T1\";
+		    }
+		    else
+		    {
+		         if(GET_CODE(operands[1])!=REG)
+		             return \"movb %X0,%T1\"; 
+ 		      	 else
+ 		      	 {
+ 		             return \"mov %T0,%T1\";
+ 		      	 }
+ 		    }
+ 		    
+          default: return \"movb %X0,%X1\";
+ 		    
+     }
+}"
+[(set_attr "length" "2,2,8,8,8")])
+
+
+
+
+;;HI mode :- Half integer move instructions(16 bit movement)
+(define_expand "movhi"
+   	   [(set (match_operand:HI 0 "general_operand" "")
+		(match_operand:HI 1 "general_operand" ""))]
+		""
+		"if (!register_operand (operand1, HImode)
+     		 && !register_operand (operand0, HImode))
+                  {
+      			operands[1] = copy_to_mode_reg (HImode, operand1);
+    		  }
+		"
+)
+ 
+
+
+		
+(define_insn "*movhi"
+  [(set (match_operand:HI 0 "general_operand_dst" "=r,<,r,r,m")
+	(match_operand:HI 1 "general_operand_src" "r>,r,i,m,r"))]
+	"TARGET_TINY||TARGET_SMALL||TARGET_LARGE"
+	"*
+	{
+	   return output_movhi_insn(operands);
+          	
+        }"
+[(set (attr "length") (symbol_ref "compute_mov_length (operands)"))])
+	
+	
+(define_expand "movsi"
+  [(set (match_operand:SI 0 "general_operand" "")
+        (match_operand:SI 1 "general_operand" ""))]
+        ""
+	"if (!register_operand (operand1, SImode)
+     	     && !register_operand (operand0, SImode))
+	     {
+	    	  operands[1] = copy_to_mode_reg (SImode, operand1);
+	     }
+	"
+)
+ 
+(define_insn "*movsi"
+  [(set (match_operand:SI 0 "general_operand_dst" "=r,<,r,r,m")
+        (match_operand:SI 1 "general_operand" "r,r,i,m,r"))]
+	""
+	"*
+	{
+	 switch(which_alternative)
+	 {
+ 	 case 4: 
+ 	     if(TARGET_LARGE)
+ 	     {
+ 	        if(GET_CODE(XEXP(operands[0],0))==SYMBOL_REF||GET_CODE(XEXP(operands[0],0))==CONST)
+ 	        {
+ 		   output_asm_insn(\"extp #PAG:%e0,#0x2\",operands);
+		    		    
+		   return \"mov pof:%f0,%f1\;mov    pof:%e0,%e1\";
+ 		   
+ 		   		   
+ 	        }
+ 		   
+ 	        else
+		{
+		   if(GET_CODE(XEXP(operands[0],0))!=PLUS&&REGNO(XEXP(operands[0],0))!=0)
+		   {
+		      output_asm_insn(\"extp %d0,#0x2\",operands);
+		   		    		   
+		   }
+		      return \"mov	%f0,%f1\;mov	%e0,%e1\"; 
+ 	        }
+ 		   
+ 	  
+ 	      }
+ 	      else
+ 	             return \"mov	%f0,%f1\;mov	%e0,%e1\"; 
+ 		   
+ 	 case 3:
+             if(TARGET_LARGE)
+ 	     {
+ 	         if(GET_CODE(XEXP(operands[1],0))==SYMBOL_REF||GET_CODE(XEXP(operands[1],0))==CONST)
+ 	         {
+ 		   
+                     output_asm_insn(\"extp #pag: %e1,#0x2\",operands);
+ 		     return \"mov %f0,pof:%f1\;mov    %e0,pof:%e1\";
+ 		   
+ 		 }
+ 		   
+ 		 else
+		 {
+		   		    		   
+		     if(GET_CODE(XEXP(operands[1],0))!=PLUS&&REGNO(XEXP(operands[1],0))!=0)
+		     {
+		        output_asm_insn(\"extp %d1,#0x2\",operands);
+		     }
+		     return \"mov	%f0,%f1\;mov	%e0,%e1\"; 
+		    		                     
+ 	         }
+ 		   		   
+ 		   
+ 	      }
+ 	      else
+ 	      {	
+ 	            if(GET_CODE(XEXP(operands[1],0))==PLUS)
+		    {
+			if(REGNO(XEXP(XEXP(operands[1],0),0))==(REGNO(operands[0])+1))
+			 return \"mov   %e0,%e1\;mov   %f0,%f1\";
+ 
+		    }
+		    return \"mov	 %f0,%f1\;mov	%e0,%e1\";
+ 		   
+ 	      }
+ 		      
+ 	  case 1:
+ 	      return \"mov	%e0,%f1\;mov	%e0,%e1\";
+ 		   
+ 	      case 0:
+ 	      {
+ 	         if(REGNO(operands[0])!=(REGNO(operands[1])+1))
+ 	   	      return \"mov     %e0,%e1\;mov      %f0,%f1\";
+ 	         else
+ 		      return \"mov     %f0,%f1\;mov      %e0,%e1\";
+ 	      }
+ 		  
+ 	  }
+ 	  if(which_alternative==2)
+          {
+		  if(GET_CODE(operands[1])==SYMBOL_REF&&TARGET_LARGE)
+		  {
+		       output_asm_insn (\"mov %f0,#PAG:%e1\",operands);
+	               output_asm_insn (\"mov %e0,#POF:%e1\",operands);
+		       return \"\";        
+		  }
+		  else
+		  { 
+		       output_asm_insn (\"mov %f0,%e1\",operands);
+		       output_asm_insn (\"mov %e0,%f1\",operands);
+		       return \"\";        
+ 		  } 
+ 		   
+ 		  }
+ 	 }"
+;;[(set_attr "length" "8,8,8,8,8")]
+[(set (attr "length") (symbol_ref "compute_mov_length (operands)"))]
+)	
+	
+ 
+ 
+ 
+ 
+ ;; Single float 32 bit move instructions
+ 
+(define_insn "movsf"
+  [(set (match_operand:SF 0 "general_operand_dst" "=r,<,r,r,m")
+        (match_operand:SF 1 "general_operand" "r,r,i,m,r"))]
+ 	""
+  	"*
+  	{
+  	 switch(which_alternative)
+         {
+  	 case 4: 
+  	      if(GET_CODE(XEXP(operands[0],0))==CONST_INT)
+	      {
+	 	       rtx p_no[2];
+		       rtx xop[2];                                                                                 
+		       xop[1]=operands[1];
+		       xop[0]=XEXP(operands[0],0);
+		       if(TARGET_LARGE)
+		       {
+		   	 if(INTVAL(XEXP(operands[0],0))>0xffff)
+		   	 {
+		    	       p_no[0]=gen_rtx_CONST_INT(HImode,INTVAL(XEXP(operands[0],0))/0x4000);
+		   	     		      		 
+		   	       xop[0]=gen_rtx_CONST_INT(HImode,INTVAL(XEXP(operands[0],0))%0x4000);
+		   	     		      		 
+		   	       operands[0]=gen_rtx_CONST_INT(HImode,INTVAL(XEXP(operands[0],0))%0x4000+2);
+		   	       output_asm_insn(\"extp %0,#0x2\",p_no);
+		   	       output_asm_insn(\"mov %i0,%e1\",xop);
+		   	       output_asm_insn(\"mov %i0,%f1\",operands);
+		   	     		      		 
+		   	       return \"\";
+		   	 }	     		      		
+		       }
+		    	       operands[0]=gen_rtx_CONST_INT(HImode,INTVAL(XEXP(operands[0],0))+2);
+		   	       output_asm_insn(\"mov %i0,%e1\",xop); 		     
+		               output_asm_insn(\"mov %i0,%f1\",operands);
+		               return \"\";
+		}
+  		   
+  	        if(TARGET_LARGE)
+	        {
+	                if(GET_CODE(XEXP(operands[0],0))==SYMBOL_REF||GET_CODE(XEXP(operands[0],0))==CONST)
+		        {
+		    	       output_asm_insn(\"extp #pag: %e0,#0x2\",operands);
+			       return \"mov pof:%f0,%f1\;mov    pof:%e0,%e1\";
+		        }
+	      		else
+	       		{
+	               		if(GET_CODE(XEXP(operands[0],0))!=PLUS)
+		       		{
+		    	       		output_asm_insn(\"extp %d0,#0x2\",operands);
+		      		}
+		       		return \"mov	%f0,%f1\;mov	%e0,%e1\"; 
+ 	       		}		   
+		    		   
+		    		   
+ 	  	}
+  		else
+  		        return \"mov	%f0,%f1\;mov	%e0,%e1\"; 
+  		   
+  	    case 3:
+	     if(TARGET_LARGE)
+ 	     {
+ 		   
+       	        if(GET_CODE(XEXP(operands[1],0))==CONST_INT)
+		{
+		        rtx xop[2];
+		        rtx p_no[2];
+		        xop[0]=operands[0];
+		        xop[1]=XEXP(operands[1],0);
+		        if(TARGET_LARGE)
+		        {
+		              if(INTVAL(XEXP(operands[1],0))>0xffff)
+		              {
+		    	 		p_no[0]=gen_rtx_CONST_INT(HImode,INTVAL(XEXP(operands[1],0))/0x4000);
+		   			xop[1]=gen_rtx_CONST_INT(HImode,INTVAL(XEXP(operands[1],0))%0x4000);
+		 		   	operands[1]=gen_rtx_CONST_INT(HImode,INTVAL(XEXP(operands[1],0))%0x4000+2);
+	   			   	output_asm_insn(\"extp %0,#0x1\",p_no);
+	        		   	output_asm_insn(\"mov %e0,%i1\",xop);
+	        		   	output_asm_insn(\"mov %f0,%i1\",operands);
+				   	return \"\";
+		              }
+		        }
+		        operands[1]=gen_rtx_CONST_INT(HImode,INTVAL(XEXP(operands[1],0))%0x4000+2);
+		        output_asm_insn(\"mov %e0,%i1\",xop);
+		        output_asm_insn(\"mov %f0,%i1\",operands);
+		        return \"\";
+	        } 
+ 		   
+ 		if(GET_CODE(XEXP(operands[1],0))==SYMBOL_REF||GET_CODE(XEXP(operands[1],0))==CONST)
+ 		{
+ 		        output_asm_insn(\"extp #pag: %e1,#0x2\",operands);
+		        return \" mov %f0,pof:%f1\;mov    %e0,pof:%e1\";
+ 	        }
+ 	        else
+	        {
+		    		   
+	 	   	if(GET_CODE(XEXP(operands[1],0))!=PLUS)
+		   	{
+		      	      output_asm_insn(\"extp %d1,#0x2\",operands);
+		    		   
+		        }
+	        	return \"mov	%f0,%f1\;mov	%e0,%e1\"; 
+ 		                     
+ 	        }
+ 	     }
+ 		   
+ 	     else
+	     {	
+  	       if(GET_CODE(XEXP(operands[1],0))==PLUS)
+               {
+              	        if(REGNO(XEXP(XEXP(operands[1],0),0)) == (REGNO(operands[0])+1)) 
+                               return \"mov   %e0,%e1\;mov   %f0,%f1\";
+                                                                                                                             
+               }
+	       return \"mov	 %f0,%f1\;mov	%e0,%e1\";
+  	     }
+  		      
+  	    case 1:
+  	       return \"mov	%e0,%f1\;mov	%e0,%e1\";
+  		   
+  	    case 0:
+  	    {
+	       if(REGNO(operands[0])!=(REGNO(operands[1])+1))
+			 return \"mov     %e0,%e1\;mov      %f0,%f1\";
+	       else
+	   		 return \"mov     %f0,%f1\;mov      %e0,%e1\";
+ 	    }
+  		  
+  	   }
+  	   if(which_alternative==2)
+  	   {
+ 	       output_asm_insn (\"mov %f0,%e1\",operands);
+ 	       output_asm_insn (\"mov %e0,%f1\",operands);
+ 	       return \"\";        
+           }
+}"
+;;[(set_attr "length" "8,8,8,8,8")]
+[(set (attr "length") (symbol_ref "compute_mov_length (operands)"))]
+)	
+	
+ 
+ 
+ ;;********************For pointer mode specially for Large Target*******
+ 
+(define_insn "movpsi"
+   [(set (match_operand:PSI 0 "general_operand_dst" "=r,r,m,r,<")
+ 	 (match_operand:PSI 1 "general_operand" "r,i,r,m,r"))]
+   "TARGET_LARGE"
+  ;;" movpsi"
+   "* return output_movpsi_insn(operands);" 
+  
+[(set_attr "length" "8,8,8,8,8")])
+    
+  
+(define_insn "addpsi3"
+  [(set (match_operand:PSI 0 "general_operand" "=r,r")
+	(plus:PSI (match_operand:PSI 1 "general_operand" "%0,0")
+	   	  (match_operand:PSI 2 "general_operand" "r,n")))]
+  "TARGET_LARGE"
+  "* return output_addpsi_insn(insn,operands,0);"
+)
+  
+  
+(define_insn "cmppsi"
+    [(set (cc0)
+          (compare (match_operand:PSI 0 "register_operand" "r,r")
+	           (match_operand:PSI 1 "general_operand" "r,n")))]
+    "TARGET_LARGE"
+    "* return output_cmppsi_insn(operands);"
+		 
+)
+		 	
+		 	
+(define_insn "truncsipsi2"
+   [(set (match_operand:PSI 0 "register_operand" "=r")
+    	 (truncate:PSI (match_operand:SI 1 "general_operand" "ri")))]
+   "TARGET_LARGE"
+   "* 
+   {
+   if(REGNO(operands[0])!=(REGNO(operands[1])+1))
+  	return \"mov %e0,%e1\;mov %f0,%f1\";
+   else
+  	return \"mov %f0,%f1\;mov %e0,%e1\";
+	
+ }")
+		 
+        
+(define_insn "extendpsisi2"
+      [(set (match_operand:SI 0 "register_operand" "=r")
+       (sign_extend:SI (match_operand:PSI 1 "register_operand" "ri")))]
+ 	"TARGET_LARGE"
+ 	"*
+ 	{
+ 	output_asm_insn(\"mov %e0,%e1\",operands);
+ 	return \"mov %f0,%f1\";
+ 	}"
+ 	)
+ 	
+ 	;;Call value RTL in PSI mode
+ 	
+ (define_insn ""
+   [(set (match_operand  0 "" "=r")
+	        (call (match_operand:PSI 1 "general_operand" "ro")
+		      (match_operand:PSI  2 "general_operand" "g"))) 
+	   ]
+         "TARGET_LARGE"
+         "* return output_call_insn(operands);"
+         [(set (attr "length") (symbol_ref "compute_call_length (operands,1)"))])
+  	
+                   
+ 
+         
+	   (define_insn ""
+	     [(call (match_operand:PSI 0 "general_operand" "or")
+	   	 (match_operand:PSI 1 "general_operand" "g"))]
+	     "TARGET_LARGE"
+	     "* return output_call_insn1(operands);"
+	      [(set (attr "length") (symbol_ref "compute_call_length (operands,0)"))]
+   )
+ 
+ 
+(define_insn "ashrpsi3"
+    [(set (match_operand:PSI 0 "register_operand" "=r")
+     (ashiftrt:PSI (match_operand:PSI 1 "register_operand" "0")
+       		   (match_operand:PSI 2 "general_operand" "rn")))]
+         "TARGET_LARGE"
+         "* {
+             if (GET_CODE (operands[2]) == CONST_INT 
+                 && INTVAL (operands[2]) >= BITS_PER_WORD)
+                  return (\"mov %0,#0     \");
+             return (\"ashr %0,%2\");
+          }"
+           [(set_attr "length" "2")])
+    
+ 
+(define_insn "ashlpsi3"
+         [(set (match_operand:PSI 0 "register_operand" "=r")
+       	(ashift:PSI (match_operand:PSI 1 "register_operand" "0")
+       		   (match_operand:PSI 2 "general_operand" "rn")))]
+         "TARGET_LARGE"
+         "* {
+             if (GET_CODE (operands[2]) == CONST_INT 
+                 && INTVAL (operands[2]) >= BITS_PER_WORD)
+                  return (\"mov %0,#0    \");
+             output_asm_insn(\"shl %0,#0x1\",operands);
+             return (\"shl %f0,%2\");
+          }"
+           [(set_attr "length" "2")])
+    
+(define_insn "subpsi3"
+   [(set (match_operand:PSI 0 "general_operand" "=r,r")
+ 	(minus:PSI (match_operand:PSI 1 "general_operand" "%0,0")
+ 		 (match_operand:PSI 2 "general_operand" "r,n")))]
+   "TARGET_LARGE"
+   "* return output_addpsi_insn(insn,operands,1);"
+  )
+  
+ ;;***************************************************************************
+ ;;--------------------------------------------------------------------------------------------------
+ ;;Following section contains instructions regarding truncate and extend
+ ;;Truncate instructions
+
+
+(define_insn "truncsihi2"
+   [(set (match_operand:HI 0 "register_operand" "=r")
+ 	(truncate:HI (match_operand:SI 1 "register_operand" "ri")))]
+   ""
+   "mov %0,%1"
+   [(set_attr "length" "2")])
+
+ 
+(define_insn "trunchiqi2"
+    [(set (match_operand:QI 0 "register_operand" "=r")
+  	(truncate:QI (match_operand:HI 1 "register_operand" "ri")))]
+    ""
+    "*
+    {
+    if(GET_CODE(operands[1])==REG&&REGNO(operands[1])==REGNO(operands[0]))
+    return \"\";    
+    if(REGNO(operands[0])<8&&REGNO(operands[1])<8)
+    return \"movb %X0,%X1\";
+    else
+    return \"mov %T0,%T1\";
+    }"
+    [(set_attr "length" "2")])
+
+ ;;Following are extend instructions
+(define_insn "extendqihi2"
+   [(set (match_operand:HI 0 "register_operand" "=r")
+ 	(sign_extend:HI (match_operand:QI 1 "register_operand" "b")))]
+   ""
+   "movbs %0,%1"
+   [(set_attr "length" "2")])
+ 
+ 
+(define_insn "zero_extendqihi2"
+   [(set (match_operand:HI 0 "register_operand" "=r")
+ 	(zero_extend:HI (match_operand:QI 1 "register_operand" "b")))]
+   ""
+  "movbz %0,%1"
+  [(set_attr "length" "2")])
+		
+;;---------------------------------------------------------------------------------------------------
+;;Following Section contains patterns for addition instructions
+;;It will be in three modes
+;;SImode : 32 bit addition
+;;HImode : 16 bit addition
+;;QImode : 8 bit addition
+
+
+ ;;  ** QI mode adition : Add two byte operands. (8 bit addition) :
+   
+   
+   
+(define_expand "addqi3"
+        [(set (match_operand:QI 0 "general_operand_src_mem" "")
+      	(plus:QI (match_operand:QI 1 "general_operand_src_mem" "")
+   		 (match_operand:QI 2 "general_operand_dst_mem" "")))]
+   
+   ""
+   "
+   {
+      if (GET_CODE (operands[0]) == MEM && (GET_CODE (XEXP (operands[0], 0))==SYMBOL_REF))
+   	    {
+   	      if(GET_CODE(operands[2])==CONST_INT)
+   	       if(INTVAL(operands[2])!=1&&INTVAL(operands[2])!=-1)
+   	        operands[2] = copy_to_mode_reg (QImode, operand2);
+   	    }
+	
+   }
+   "
+   )
+   
+(define_insn "*addqi3"
+           [(set (match_operand:QI 0 "general_operand_src_mem" "=b,b,b,S")
+         	(plus:QI (match_operand:QI 1 "general_operand_src_mem" "%0,0,0,0")
+      		 (match_operand:QI 2 "general_operand_dst_mem" "b,n,S,i")))]
+      
+   ""
+   "*
+   {
+      if(which_alternative<2)
+          {
+         	output_asm_insn (\"addb %X0,%X2\", operands); 
+         	return \"\";
+          }
+         else if(which_alternative==2)
+         {
+          if(TARGET_LARGE)
+           {
+             	  output_asm_insn (\"extp #PAG:%2,#0x1\",operands);
+                     return \"addb %X0,POf:%2\";  
+           }
+          else
+          		  output_asm_insn (\"addb %X0,%X2\", operands); 
+         }
+         else 
+         {
+         
+         	if(TARGET_LARGE)
+         	 {
+         	  
+         	  if(INTVAL(operands[2])==1)
+         	  {
+         	  return \"subb POF:%0,ONES\";
+         	  output_asm_insn (\"extp #PAG:%0,#0x1\",operands);
+         	  }
+         	  else if(INTVAL(operands[2])==-1)
+                  {
+                  output_asm_insn (\"extp #PAG:%0,#0x1\",operands);
+                  return \"addb POF:%0,ONES\";
+         	  } 
+         	  else
+         	  return \"\";
+         	 
+         	 }
+           else
+             {
+         	  if(INTVAL(operands[2])==1)
+         	  return \"subb %0,ONES\";
+         	  else if(INTVAL(operands[2])==-1)
+         	  return \"addb %0,ONES\";
+                  else
+                  return \"\";
+             }
+         }
+   
+    
+   }"
+   [(set (attr "length") (symbol_ref "compute_add_length (operands)"))]
+   )
+   
+   
+   
+ ;;Operand constraint X : It is related to substituting small register names like r4l, r4h etc.
+ 
+ ;; Right now no attributes are used 
+   
+ 
+ 
+ ;;   ** HI mode addition : Add two word operands (16 bit addition)
+ 
+   
+   ;;In the following case last operand is regarding instruction in which 0th operand is not matched 
+   ;;either with 1st or 2nd operand so we need to move that operand in operand 0 first and then perform addition
+   
+   
+(define_expand "addhi3"
+     [(set (match_operand:HI 0 "general_operand_src_mem" "")
+              	(plus:HI (match_operand:HI 1 "general_operand_src_mem" "")
+     		 (match_operand:HI 2 "general_operand_dst_mem" "")))]
+	""
+	"
+	{
+	   if (GET_CODE (operands[0]) == MEM && (GET_CODE (XEXP (operands[0], 0))==SYMBOL_REF))
+	    {
+	      
+	      if(GET_CODE(operands[2])==CONST_INT)
+	       if(INTVAL(operands[2])!=1&&INTVAL(operands[2])!=-1)
+	        operands[2] = copy_to_mode_reg (HImode, operand2);
+	    }
+	  } 
+	"
+  )
+	
+(define_insn "*addhi3"
+      [(set (match_operand:HI 0 "general_operand_src_mem" "=r,r,r,S,S")
+         	(plus:HI (match_operand:HI 1 "general_operand_src_mem" "%0,0,0,0,0")
+		 (match_operand:HI 2 "general_operand_dst_mem" "r,n,S,i,r")))]
+		 
+   ""
+   "*
+   {
+     int temp;
+     if(which_alternative==4)
+      {
+      if(TARGET_LARGE)
+             {
+               	  
+               	  output_asm_insn (\"extp #PAG:%0,#0x1\",operands);
+                  return \"add POF:%0,%2\";  
+             }
+            else
+      		  return \"add %0,%2\"; 
+      }
+      
+      if(which_alternative<2)
+      {
+     	output_asm_insn (\"add %0,%2\", operands); 
+     	return \"\";
+      }
+     else if(which_alternative==2)
+     {
+      if(TARGET_LARGE)
+       {
+         	  output_asm_insn (\"extp #PAG:%2,#0x1\",operands);
+                 return \"add %0,POf:%2\";  
+       }
+      else
+      		  return \"add %0,%2\"; 
+     }
+     else if(which_alternative==3)
+     {
+     
+     	if(TARGET_LARGE)
+     	 {
+     	  
+     	  
+     	  if(INTVAL(operands[2])==1)
+     	  {
+     	/* if(!MEM_SCALAR_P(operands[1])) */
+     	  output_asm_insn (\"extp #PAG:%0,#0x1\",operands);
+     	  return \"sub POF:%0,ONES\";
+          
+          }
+          else if(INTVAL(operands[2])==-1)
+          {
+          output_asm_insn (\"extp #PAG:%0,#0x1\",operands);
+          return \"add POF:%0,ONES\";
+          
+          }
+          else
+          return \"\";
+     	 }
+       else
+         {
+     	  if(INTVAL(operands[2])==1)
+     	  return \"sub %0,ONES\";
+     	  else if(INTVAL(operands[2])==-1)
+     	  return \"add %0,ONES\";
+     	  else
+     	  return \"\";
+         }
+     }
+   }
+   "
+   [(set (attr "length") (symbol_ref "compute_add_length (operands)"))])
+  
+   
+   
+   ;;  ** SI mode addition : Add two double word operands (32 bit addition)
+   
+   ;; Here constraint "f" is used which is very useful in outputting higher 16 bits addition
+   ;; It should increment register no by one and use new register no in the addition
+(define_insn "addsi3"
+         [(set (match_operand:SI 0 "general_operand_src_mem" "=r,r,r,S")
+            	(plus:SI (match_operand:SI 1 "general_operand_dst_mem" "%0,0,0,0")
+   		 (match_operand:SI 2 "general_operand_dst_mem" "r,n,S,r")))]
+  
+   ""
+                                     
+   "*
+      {
+                                  
+        if(which_alternative==0)  
+         {
+           output_asm_insn (\"add %e0,%e2\",operands);
+           return \"addc %f0,%f2\";
+         }
+                                  
+        else if(which_alternative==1)                      
+         {
+           rtx xop[3];
+           xop[0]=operands[0];
+           xop[1]=gen_rtx_CONST_INT( VOIDmode,
+				 INTVAL (operands[2]) >> 16) ;                                          
+         
+           xop[2] = gen_rtx_CONST_INT ( VOIDmode,
+				 INTVAL (operands[2]) & 0xffff);
+                      output_asm_insn (\"add %e0,%2\",xop);
+	              output_asm_insn (\"addc %f0,%1\",xop);
+                        return \"\";    
+         
+         }
+         
+        else  if(which_alternative==2)
+        {
+          if(TARGET_LARGE)
+           {
+             output_asm_insn(\"extp #PAG:%2,#0x2\",operands);
+             output_asm_insn(\"add %e0,POF:%e2\",operands);
+             return \"addc %f0,POF:%f2\";
+           }
+          else
+           {
+             output_asm_insn(\"add %e0,%e2\",operands);
+             return \"addc %f0,%f2\";
+          
+           }
+        }
+        else if (which_alternative==3)
+        {
+          if(TARGET_LARGE)
+           {
+              output_asm_insn(\"extp #PAG:%0,#0x2\",operands);
+	      output_asm_insn(\"add POF:%e0,%e2\",operands);
+	      return \"addc POF:%f0,%f2\";
+           
+           }
+          else
+           {
+              output_asm_insn(\"add %e0,%e2\",operands);
+	      return \"addc %f0,%f2\";
+          
+           }
+        }
+
+      }"
+   
+[(set (attr "length") (symbol_ref "compute_add_length (operands)"))])
+   
+   
+   
+   ;;-------------------------------------------------------------------------------------------------
+   ;;Following Section contains patterns for subtraction instructions
+   ;;It will be in three modes
+   ;;SImode : 32 bit subtraction
+   ;;HImode : 16 bit subtraction
+   ;;QImode : 8 bit subtraction
+      
+   
+   ;;QI mode subtraction
+(define_insn "subqi3"
+      [(set (match_operand:QI 0 "register_operand" "=b,b")
+    	(minus:QI (match_operand:QI 1 "register_operand" "0,0")
+    		 (match_operand:QI 2 "general_operand_dst_mem" "b,n")))]
+      ""
+    "*
+    {
+       switch(which_alternative)
+        {
+         case 0:
+             return \"subb %X0,%X2\";
+  	 case 1:
+  	      return \"subb %X0,%2\";
+         case 2:
+              if(TARGET_LARGE)
+              {
+                   output_asm_insn(\"extp #PAG:%2,#0x1\",operands);
+	           return \"subb %X0 , POF:%2\";
+            
+              }
+              else
+               return \"subb %X0,%X2\";
+        }
+    }"
+    [(set (attr "length") (symbol_ref "compute_add_length (operands)"))]
+    )
+    
+    
+    ;;HI mode subtraction
+    
+    
+    
+(define_insn "subhi3"
+     [(set (match_operand:HI 0 "register_operand" "=r,r,r,S")
+        	(minus:HI (match_operand:HI 1 "register_operand" "0,0,0,0")
+        		 (match_operand:HI 2 "general_operand_dst_mem" "r,n,S,r")))]
+      ""
+      "*
+      {
+      	if(which_alternative==3)
+      	{
+      	       if(TARGET_LARGE) 
+	          {
+	            output_asm_insn(\"extp #PAG:%0,#0x1\",operands);
+	            return \"sub POF:%0 , %2\";
+	          }
+	       else
+                     return \"sub %0 , %2\";
+      	}
+      	else if(which_alternative<2)
+      	        	    
+      		    return \"sub %0 , %2\";
+      			
+      	else
+      	  {
+                    if(TARGET_LARGE) 
+                       {
+                       output_asm_insn(\"extp #PAG:%2,#0x1\",operands);
+                       return \"sub %0 , POF:%2\";
+                       }
+                    else
+                       return \"sub %0 , %2\";
+          }
+      }"
+      [(set (attr "length") (symbol_ref "compute_add_length (operands)"))]
+     )
+      
+      
+     ;; SI mode subtraction
+(define_insn "subsi3"
+          [(set (match_operand:SI 0 "general_operand_src_mem" "=r,r,r,S")
+        	(minus:SI (match_operand:SI 1 "general_operand_src_mem" "0,0,0,0")
+        		 (match_operand:SI 2 "general_operand_dst_mem" "r,n,S,r")))]
+    ""
+    "*
+      {
+     if(which_alternative==0)
+      {
+         output_asm_insn (\"sub %e0,%e2\",operands);
+	 output_asm_insn (\"subc %f0,%f2\",operands);  
+         return \"\";   
+      }
+     else if(which_alternative==1)
+      {
+          rtx xop[3];
+               xop[0]  = operands[0];
+	       xop[1] = gen_rtx_CONST_INT (VOIDmode,
+				 INTVAL (operands[2]) >> 16);
+	       xop[2] = gen_rtx_CONST_INT ( VOIDmode,
+				 INTVAL (operands[2]) & 0xffff);       
+      
+               output_asm_insn (\"sub  %e0 , %2 \",operands);
+               output_asm_insn (\"subc  %f0 , %1\",operands);
+               return \"\";
+                 
+      } 
+     else if(which_alternative==2)
+     {
+           if(TARGET_LARGE)
+           {
+             output_asm_insn(\"extp #PAG:%2,#0x2\",operands);
+             output_asm_insn(\"sub %e0,POF:%e2\",operands);
+             return \"subc %f0,POF:%f2\";
+           }
+          else
+           {
+             output_asm_insn(\"sub %e0,%e2\",operands);
+             return \"subc %f0,%f2\";
+          
+           } 
+     }
+     else if(which_alternative==3)
+     {
+            if(TARGET_LARGE)
+                  {
+              output_asm_insn(\"extp #PAG:%0,#0x2\",operands);
+       	      output_asm_insn(\"sub POF:%e0,%e2\",operands);
+       	      return \"subc POF:%f0,%f2\";
+                  
+                  }
+                 else
+                  {
+                     output_asm_insn(\"sub %e0,%e2\",operands);
+       	      	     return \"subc %f0,%f2\";
+                 
+           }
+     }
+    }
+    "
+    [(set (attr "length") (symbol_ref "compute_add_length (operands)"))])
+     
+     
+  ;;---------------------------------------------------------------------------------------------------   
+  
+  ;; Folowing section generates multiply instructions , in
+  
+  ;; HI mode : Word multiply
+  ;; SI mode : Double word multiply  
+  
+  
+  ;; HI mode multiplication
+(define_insn "umulqihi3"
+    [(set (match_operand:HI 0 "register_operand" "=r")
+  	(mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
+  		 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
+    ""
+  "*
+  {
+    	output_asm_insn (\"movbz %T2,%X2\", operands);
+    	output_asm_insn (\"movbz %T1,%X1\", operands);
+    	output_asm_insn (\"atomic #0x1\", operands);
+  	output_asm_insn (\"mulu %T1,%T2\", operands);
+  	output_asm_insn (\"mov %T0,MDL\", operands);
+  	return \"\";
+ 
+  }"
+  [(set_attr "length" "12")])
+  
+(define_insn "mulpsi3"
+[(set (match_operand:PSI 0 "register_operand" "=r")
+      (mult :PSI (match_operand:PSI 1 "register_operand" "%0")
+                 (match_operand:PSI 2 "register_operand" "r")
+      )
+ )]
+"TARGET_LARGE"
+"*{
+return \"\";
+}
+"  
+)
+(define_insn "mulhi3"
+    [(set (match_operand:HI 0 "register_operand" "=r")
+  	(mult:HI (match_operand:HI 1 "register_operand" "%0")
+  		 (match_operand:HI 2 "register_operand" "r")))]
+    ""
+    "* {
+  	
+  	output_asm_insn (\"atomic #0x1\", operands);
+  	output_asm_insn (\"mul %1,%2\", operands);
+  	output_asm_insn (\"mov %0,MDL\", operands);
+  	return \"\";
+
+   } "
+   [(set_attr "length" "8")])
+  
+(define_insn "mulqi3"
+      [(set (match_operand:QI 0 "register_operand" "=r")
+    	(mult:QI (match_operand:QI 1 "register_operand" "%0")
+    		 (match_operand:QI 2 "register_operand" "r")))]
+      ""
+      "* {
+    	
+    	output_asm_insn (\"movbs %T2,%X2\", operands);
+    	output_asm_insn (\"movbs %T1,%X1\", operands);
+    	output_asm_insn (\"atomic #0x1\", operands);
+    	output_asm_insn (\"mul %T1,%T2\", operands);
+    	output_asm_insn (\"mov %T0,MDL\", operands);
+    	return \"\";
+  
+     } " 
+     [(set_attr "length" "12")])
+    
+  
+   
+   
+   ;;SI mode multiplication
+   
+(define_insn "mulsi3"
+       [(set (match_operand:SI 0 "register_operand" "=r")
+     	(mult:SI (match_operand:SI 1 "register_operand" "%0")
+     		 (match_operand:SI 2 "register_operand" "r")))]
+       ""
+       "* {
+     	   	   
+	   	   output_asm_insn (\"atomic #0x1\", operands);
+	   	   output_asm_insn (\"mulu %f0,%e2\",operands);
+	   	   output_asm_insn (\"mov %f0,MDL\",operands);
+	   	   
+	   	   output_asm_insn (\"atomic #0x1\", operands);
+	   	   output_asm_insn (\"mulu %f2,%e0\",operands);
+	   	   output_asm_insn (\"add %f0,MDL\",operands);
+	   	   output_asm_insn (\"atomic #0x1\", operands);
+	   	   output_asm_insn (\"mulu %e0,%e2\",operands);
+	   output_asm_insn (\"add %f0,MDH\",operands);
+	   output_asm_insn (\"mov %e0,MDL\",operands);
+	return \"\";
+     	
+   } " 
+   [(set_attr "length" "28")])
+  
+  
+  
+  
+  
+  
+  
+  ;;--------------------------------------------------------------------------------------------------
+  ;;Following section generates division and modulo instruction in
+  ;;HI mode : That is 16 bit  by 16 bit division is carried out
+  ;;Quotient is stored in register MDL and remainder is stored in register MDH
+  
+  
+  ;;Signed 16 bit division
+  
+  
+(define_insn "divhi3"
+    [(set (match_operand:HI 0 "register_operand" "=r")
+  	(div:HI (match_operand:HI 1 "register_operand" "r")
+  		(match_operand:HI 2 "register_operand" "r")))]
+    ""
+    "* {
+  	output_asm_insn (\"mov MDL,%1\", operands);
+        output_asm_insn (\"atomic #0x1\", operands);
+  	output_asm_insn (\"div %2\", operands);
+  	output_asm_insn (\"mov %0,MDL\", operands);
+  	return \"\";
+  } " 
+  [(set_attr "length" "10")])
+  
+  ;;Unsigned 16 bit division
+  
+(define_insn "udivhi3"
+    [(set (match_operand:HI 0 "register_operand" "=r")
+  	(udiv:HI (match_operand:HI 1 "register_operand" "r")
+  		(match_operand:HI 2 "register_operand" "r")))]
+    ""
+    "* {
+  	output_asm_insn (\"mov MDL,%1\", operands);
+        output_asm_insn (\"atomic #0x1\", operands);
+  	output_asm_insn (\"divu %2\", operands);
+  	output_asm_insn (\"mov %0,MDL\", operands);
+  	return \"\";
+  } " 
+  [(set_attr "length" "10")])
+  
+  
+(define_insn "modhi3"
+    [(set (match_operand:HI 0 "register_operand" "=r")
+  	(mod:HI (match_operand:HI 1 "register_operand" "r")
+  		(match_operand:HI 2 "register_operand" "r")))]
+    ""
+    "* {
+  	output_asm_insn (\"mov MDL,%1\", operands);
+        output_asm_insn (\"atomic #0x1\", operands);
+  	output_asm_insn (\"div %2\", operands);
+  	output_asm_insn (\"mov %0,MDH\", operands);
+  	return \"\";
+  } " 
+  [(set_attr "length" "10")])
+  
+  
+(define_insn "umodhi3"
+    [(set (match_operand:HI 0 "register_operand" "=r")
+  	(umod:HI (match_operand:HI 1 "register_operand" "r")
+  		(match_operand:HI 2 "register_operand" "r")))]
+    ""
+    "* {
+  	output_asm_insn (\"mov MDL,%1\", operands);
+        output_asm_insn (\"atomic #0x1\", operands);
+  	output_asm_insn (\"divu %2\", operands);
+  	output_asm_insn (\"mov %0,MDH\", operands);
+  	return \"\";
+} " 
+[(set_attr "length" "10")])
+
+
+;;---------------------------------------------------------------------------------------------------
+
+;; Following section generates assebly instructions regarding logical operations 
+;; such as negation , complement ,and , or and xor ,negation ,complement etc.
+ 
+;; Right now support to bclr and bset instructions is  added through and/or instructions  
+;;And instruction in 
+;; QI mode : byte anding
+;; HI mode : Word anding
+;; SI mode : Double word anding
+
+;;QI mode and instruction
+
+(define_insn "andqi3"
+  [(set (match_operand:QI 0 "register_operand" "=b,b")
+	(and:QI (match_operand:QI 1 "register_operand" "%0,0")
+		 (match_operand:QI 2 "general_operand" "b,n")))]
+  ""
+  "* return op_and_insn(operands);"
+  [(set_attr "length" "2,4")])
+
+
+;;HI mode and instruction
+
+(define_insn "andhi3"
+  [(set (match_operand:HI 0 "general_operand" "=r,r")
+	(and:HI (match_operand:HI 1 "general_operand" "%0,0")
+		 (match_operand:HI 2 "general_operand" "r,n")))]
+  ""
+  "
+  and %0,%2
+   "
+   [(set_attr "length" "2,4")]) 
+  
+  
+ ;; SI mode and instruction 
+ 
+ (define_insn "andsi3"
+   [(set (match_operand:SI 0 "general_operand" "=r,r")
+   	(and:SI (match_operand:SI 1 "general_operand" "%0,0")
+   		 (match_operand:SI 2 "general_operand" "r,n")))]
+  
+ ""
+   "* {
+         
+         if (REG_P (operands[2]))
+         {
+ 	       output_asm_insn (\"and %e0,%e2\",operands);
+ 	       output_asm_insn (\"and %f0,%f2\",operands);
+         }
+         else
+         {
+               rtx xop[3];
+               xop[0]  = operands[0];
+ 	       xop[1] = gen_rtx_CONST_INT ( VOIDmode,
+ 				 INTVAL (operands[2]) >> 16);
+ 	       xop[2] = gen_rtx_CONST_INT ( VOIDmode,
+ 				 INTVAL (operands[2]) & 0xffff);
+ 	       output_asm_insn (\"and %e0,%2\",xop);
+ 	       output_asm_insn (\"and %f0,%1\",xop);
+          }
+ 	return \"\";
+  } "
+ [(set_attr "length" "4,8")])
+  
+  
+  
+  ;; Following section generates OR instructions in
+  ;; QI mode : byte oring
+  ;; HI mode : Word oring
+  ;; SI mode : Double word oring
+
+
+(define_insn "iorsi3"
+    [(set (match_operand:SI 0 "register_operand" "=r,r")
+    	  (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
+  		  (match_operand:SI 2 "general_operand" "r,n")))]
+    ""
+    "* {
+          CC_STATUS_INIT;
+          if (REG_P (operands[2]))
+          {
+  	       output_asm_insn (\"or %e0,%e2\",operands);
+  	       output_asm_insn (\"or %f0,%f2\",operands);
+          }
+          else
+          {
+               rtx xop[3];
+               xop[0]  = operands[0];
+  	       xop[1] = gen_rtx_CONST_INT ( VOIDmode,
+  				 INTVAL (operands[2]) >> 16);
+  	       xop[2] = gen_rtx_CONST_INT ( VOIDmode,
+  				 INTVAL (operands[2]) & 0xffff);
+  	       output_asm_insn (\"or %e0,%2\",xop);
+  	       output_asm_insn (\"or %f0,%1\",xop);
+          }
+  	return \"\";
+        } "
+[(set_attr "length" "4,8")])
+  
+  
+(define_insn "iorhi3"
+    [(set (match_operand:HI 0 "general_operand" "=r,r")
+  	(ior:HI (match_operand:HI 1 "general_operand" "%0,0")
+  		 (match_operand:HI 2 "general_operand" "r,n")))]
+    ""
+    "or %0,%2"
+    [(set_attr "length" "2,4")])
+  
+(define_insn "iorqi3"
+    [(set (match_operand:QI 0 "register_operand" "=b,b")
+  	(ior:QI (match_operand:QI 1 "register_operand" "%0,0")
+  		 (match_operand:QI 2 "general_operand" "b,n")))]
+    ""
+  "* return op_or_insn(operands);"
+  [(set_attr "length" "2,4")])
+  
+    
+    
+    ;; Following section generates XOR instructions in
+    ;; QI mode : byte xoring
+    ;; HI mode : Word xoring
+    ;; SI mode : Double word xoring
+
+  
+  
+  
+(define_insn "xorsi3"
+    [(set (match_operand:SI 0 "register_operand" "=r,r")
+  	(xor:SI (match_operand:SI 1 "register_operand" "%0,0")
+  		(match_operand:SI 2 "general_operand" "r,n")))]
+    ""
+    "* {
+          
+        if (REG_P (operands[2]))
+        {
+  	  output_asm_insn (\"xor %e0,%e2\",operands);
+  	  output_asm_insn (\"xor %f0,%f2\",operands);
+        }
+        else
+        {
+               rtx xop[3];
+               xop[0]  = operands[0];
+  	       xop[1] = gen_rtx_CONST_INT ( VOIDmode,
+  				 INTVAL (operands[2]) >> 16);
+  	       xop[2] = gen_rtx_CONST_INT ( VOIDmode,
+  				 INTVAL (operands[2]) & 0xffff);
+  	       output_asm_insn (\"xor %e0,%2\",xop);
+  	       output_asm_insn (\"xor %f0,%1\",xop);
+        }
+   
+  	return \"\";
+    } "
+     [(set_attr "length" "4,8")])
+  
+  
+(define_insn "xorhi3"
+    [(set (match_operand:HI 0 "general_operand" "=r,r")
+  	(xor:HI (match_operand:HI 1 "general_operand" "%0,0")
+  		 (match_operand:HI 2 "general_operand" "r,n")))]
+    ""
+    "xor %0,%2"
+     [(set_attr "length" "2,4")])
+  
+(define_insn "xorqi3"
+    [(set (match_operand:QI 0 "register_operand" "=b,b")
+  	(xor:QI (match_operand:QI 1 "register_operand" "%0,0")
+  		 (match_operand:QI 2 "general_operand" "b,b")))]
+    ""
+  "xorb %X0,%X2"
+   [(set_attr "length" "2,4")])
+  
+  
+  
+  
+  ;;Following section generates negation instructions in
+  ;;HI mode : word negation
+  ;;QI mode : byte negation
+  ;;SI mode : double word negation
+  
+  
+  
+  
+  
+  ;;HI mode negation
+  
+(define_insn "neghi2"
+    [(set (match_operand:HI 0 "register_operand" "=r")
+  	(neg:HI (match_operand:HI 1 "register_operand" "0")))]
+    ""
+    "neg %0"
+     [(set_attr "length" "2")])
+  
+  
+  ;;QI mode negation
+  
+(define_insn "negqi2"
+    [(set (match_operand:QI 0 "register_operand" "=r")
+  	(neg:QI (match_operand:QI 1 "register_operand" "0")))]
+    ""
+  "negb %X0"
+ [(set_attr "length" "2")])
+  
+  ;;SI mode negation
+  
+(define_insn "negsi2"
+      [(set (match_operand:SI 0 "register_operand" "=r")
+    	(neg:SI (match_operand:SI 1 "register_operand" "0")))]
+      ""
+      "*
+       {
+         output_asm_insn (\"neg %0\",operands);
+         output_asm_insn (\"cpl %f0\",operands);
+         return \"addc %f0,#0\";
+       }
+      "
+ [(set_attr "length" "8")])
+  
+  
+  ;;sf mode negation
+  
+(define_insn "negsf2"
+    [(set (match_operand:SF 0 "register_operand" "=r")
+  	(neg:SF (match_operand:SF 1 "register_operand" "0")))]
+    ""
+    "bmovn %f0.15,%f0.15"		
+ [(set_attr "length" "4")])
+  
+  
+  ;;Following section generates 1's Complement instruction in
+  ;;QI mode : byte complement
+  ;;HI mode : word complement
+  ;;SI mode : double word complement
+  
+  
+  ;;SI mode complement
+  
+(define_insn "one_cmplsi2"
+    [(set (match_operand:SI 0 "register_operand" "=r")
+  	(not:SI (match_operand:SI 1 "register_operand" "0")))]
+    ""
+    "* {
+          
+        output_asm_insn (\"cpl %0\",operands);
+  	output_asm_insn (\"cpl %f0\",operands);
+  	return \"\";
+    } "
+ [(set_attr "length" "4")])
+  
+  
+  ;;HI mode complement
+  
+(define_insn "one_cmplhi2"
+    [(set (match_operand:HI 0 "register_operand" "=r")
+  	(not:HI (match_operand:HI 1 "register_operand" "0")))]
+    ""
+    "cpl %0"
+ [(set_attr "length" "2")])
+  
+  
+  ;;QI mode complement
+  
+(define_insn "one_cmplqi2"
+    [(set (match_operand:QI 0 "register_operand" "=r")
+  	(not:QI (match_operand:QI 1 "register_operand" "0")))]
+    ""
+  "cplb %X0"
+ [(set_attr "length" "2")])
+  
+   
+   
+   ;; Following section generates instruction regarding absolute
+   
+(define_insn "abssf2"
+     [(set (match_operand:SF 0 "register_operand" "=r")
+   	(abs:SF (match_operand:SF 1 "register_operand" "0")))]
+     ""
+    "bclr %f0.15"
+ [(set_attr "length" "2")])
+    
+    
+    ;;--------------------------------------------------------------------------------------------
+    ;;Following section generates  shifting instructions like
+    ;; Arithmatic shift left
+    ;; Shift left/right in
+    ;; HImode -  That is for word operand
+    
+    ;;Arithmatic shift left 
+    
+(define_insn "ashlhi3"
+      [(set (match_operand:HI 0 "register_operand" "=r")
+    	(ashift:HI (match_operand:HI 1 "register_operand" "0")
+    		   (match_operand:HI 2 "general_operand" "rn")))]
+      ""
+      "* {
+          if (GET_CODE (operands[2]) == CONST_INT 
+              && INTVAL (operands[2]) >= BITS_PER_WORD)
+               return (\"mov %0,#0    \");
+           if(INTVAL (operands[2]) < 0)
+	                 return (\"mov %0,#0    \");  
+          
+          return (\"shl %0,%2;ashl insn\");
+       }"
+ [(set_attr "length" "2")])
+    
+    ;;Arithmatic shift right in HImode
+    
+(define_insn "ashrhi3"
+      [(set (match_operand:HI 0 "register_operand" "=r")
+    	(ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
+    		   (match_operand:HI 2 "general_operand" "rn")))]
+      ""
+      "* {
+          if (GET_CODE (operands[2]) == CONST_INT 
+              && INTVAL (operands[2]) >= BITS_PER_WORD)
+               return (\"mov %0,#0     \");
+           if(INTVAL (operands[2]) < 0)
+               return (\"mov %0,#0    \");  
+          return (\"ashr %0,%2\");
+       }"
+ [(set_attr "length" "2")])
+    
+    
+    ;;Logical shift right in HImode
+    
+(define_insn "lshrhi3"
+      [(set (match_operand:HI 0 "register_operand" "=r")
+    	(lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
+    		   (match_operand:HI 2 "general_operand" "rn")))]
+      ""
+      "* {
+          if (GET_CODE (operands[2]) == CONST_INT 
+              && INTVAL (operands[2]) >= BITS_PER_WORD)
+               return (\"mov %0,#0    \");
+           if(INTVAL (operands[2]) < 0)
+               return (\"mov %0,#0    \");  
+          return (\"shr %0,%2\");
+   }"
+   [(set_attr "length" "2")] )
+    
+    
+    ;;----------------------------------------------------------------------------------------------
+    ;;Following part generates the rotate (left/right) instructions
+    ;;In HImode - Word operand only
+    
+    
+    ;;Rotate right in HImode
+(define_insn "rotrhi3"
+          [(set (match_operand:HI 0 "register_operand" "=r")
+        	(rotatert:HI (match_operand:HI 1 "register_operand" "0")
+        		   (match_operand:HI 2 "general_operand" "rn")))]
+          ""
+          "* {
+              if (GET_CODE (operands[2]) == CONST_INT 
+                  && INTVAL (operands[2]) >= BITS_PER_WORD)
+                   return (\"mov %0,#0  \");
+              return (\"ror %0,%2\");
+       }"
+       [(set_attr "length" "2")])
+    
+    
+    ;;Rotate left in HImode
+    
+(define_insn "rotlhi3"
+               [(set (match_operand:HI 0 "register_operand" "=r")
+             	(rotate:HI (match_operand:HI 1 "register_operand" "0")
+             		   (match_operand:HI 2 "general_operand" "rn")))]
+               ""
+               "* {
+                   if (GET_CODE (operands[2]) == CONST_INT 
+                       && INTVAL (operands[2]) >= BITS_PER_WORD)
+                        return (\"mov %0,#0    \");
+                   return (\"rol %0,%2\");
+            }"
+           [(set_attr "length" "2")]  )
+    
+    
+    
+    ;;------------------------------------------------------------------------------------------------
+    ;;Following section outputs various jump instructions
+    ;;Here l is used for directly printing lable reference
+    ;; call output_addr_const function which will print the label 
+    
+    ;;Jump if equal
+(define_insn "beq"
+      [(set (pc)
+    	(if_then_else (eq (cc0)
+    			  (const_int 0))
+    		      (label_ref (match_operand 0 "" ""))
+    		      (pc)))
+      ]
+      ""
+      "*
+      {
+      
+     /* TBD : This comment part for jump insns is still under review */
+      if(get_attr_length(insn)==2&&optimize<2)
+            return \"jmpr cc_EQ,%l0\";
+      else  
+            return \"jmpa cc_EQ,%l0\";            
+                    
+      }"
+      [(set_attr "type" "branch")])
+    
+    ;;Jump if not equal to
+  
+    
+    
+    
+(define_insn "bne"
+      [(set (pc)
+    	(if_then_else (ne (cc0)
+    			  (const_int 0))
+    		      (label_ref (match_operand 0 "" ""))
+    		      (pc)))
+      ]
+      ""
+      "*
+           {
+          
+          if(get_attr_length(insn)==2&&optimize<2)
+                 return \"jmpr cc_NE,%l0\";
+          else  
+                 return \"jmpa cc_NE,%l0\";            
+                   
+           }"
+     
+            [(set_attr "type" "branch")])
+    
+    ;;Jump if greater than
+    
+    
+    
+    
+(define_insn "bgt"
+      [(set (pc)
+    	(if_then_else (gt (cc0)
+    			  (const_int 0))
+    		      (label_ref (match_operand 0 "" ""))
+    		      (pc)))]
+      ""
+      "*
+      {
+      if(get_attr_length (insn)==2&&optimize<2)
+       return \"jmpr cc_SGT,%l0\";
+      else  
+      return \"jmpa cc_SGT,%l0\";
+      
+      }"
+     [(set (attr "length") (if_then_else (and (ge (minus (match_dup 0) (pc))
+				(const_int -126))
+			    (le (minus (match_dup 0) (pc))
+				(const_int 126)))
+		       (const_int 2) (const_int 4)))]
+		)
+    
+    ;;Jump if unsigned greater than
+    
+(define_insn "bgtu"
+      [(set (pc)
+    	(if_then_else (gtu (cc0)
+    			   (const_int 0))
+    		      (label_ref (match_operand 0 "" ""))
+    		      (pc)))
+      ]
+      ""
+      "*
+                 {
+                 if(get_attr_length(insn)==2&&optimize<2)
+                       return \"jmpr cc_UGT,%l0\";
+                 else  
+                       return \"jmpa cc_UGT,%l0\";            
+                 }"
+     
+          [(set_attr "type" "branch")])
+    
+    ;;Jump if less than
+    
+(define_insn "blt"
+      [(set (pc)
+    	(if_then_else (lt (cc0)
+    			  (const_int 0))
+    		      (label_ref (match_operand 0 "" ""))
+    		      (pc)))
+      ]
+      ""
+      "*
+                 {
+                 if(get_attr_length(insn)==2&&optimize<2)
+                       return \"jmpr cc_SLT,%l0\";
+                 else  
+                       return \"jmpa cc_SLT,%l0\";            
+                 }"
+     
+      [(set_attr "type" "branch")])
+    
+    ;;Jump if unsigned less than
+    
+(define_insn "bltu"
+      [(set (pc)
+    	(if_then_else (ltu (cc0)
+    			   (const_int 0))
+    		      (label_ref (match_operand 0 "" ""))
+    		      (pc)))
+      ]
+      ""
+      "*
+                 {
+                 if(get_attr_length(insn)==2&&optimize<2)
+                       return \"jmpr cc_ULT,%l0\";
+                 else  
+                       return \"jmpa cc_ULT,%l0\";            
+                 }"
+     
+      [(set_attr "type" "branch")])
+    
+    ;;Jump if greater than or equal to
+(define_insn "bge"
+      [(set (pc)
+    	(if_then_else (ge (cc0)
+    			  (const_int 0))
+    		      (label_ref (match_operand 0 "" ""))
+    		      (pc)))
+      ]
+      ""
+      "*
+                 {
+                 if(get_attr_length(insn)==2&&optimize<2)
+                       return \"jmpr cc_SGE,%l0\";
+                 else  
+                       return \"jmpa cc_SGE,%l0\";            
+                 }"
+     
+      [(set_attr "type" "branch")])
+    
+    ;;Jump if unsigned greater than equal to
+(define_insn "bgeu"
+      [(set (pc)
+    	(if_then_else (geu (cc0)
+    			   (const_int 0))
+    		      (label_ref (match_operand 0 "" ""))
+    		      (pc)))
+      ]
+      ""
+      "*
+                 {
+                 if(get_attr_length(insn)==2&&optimize<2)
+                       return \"jmpr cc_UGE,%l0\";
+                 else  
+                       return \"jmpa cc_UGE,%l0\";            
+                 }"
+     
+      [(set_attr "type" "branch")])
+    
+    ;;Jump if less than or equal to
+(define_insn "ble"
+      [(set (pc)
+    	(if_then_else (le (cc0)
+    			  (const_int 0))
+    		      (label_ref (match_operand 0 "" ""))
+    		      (pc)))
+      ]
+      ""
+      "*
+                 {
+                 if(get_attr_length(insn)==2&&optimize<2)
+                       return \"jmpr cc_SLE,%l0\";
+                 else  
+                       return \"jmpa cc_SLE,%l0\";            
+                 }"
+     
+      [(set_attr "type" "branch")])
+    
+    ;;Jump if unsigned less than or equal to
+(define_insn "bleu"
+      [(set (pc)
+    	(if_then_else (leu (cc0)
+    			   (const_int 0))
+    		      (label_ref (match_operand 0 "" ""))
+    		      (pc)))
+      ]
+      ""
+      "*
+                 {
+                 if(get_attr_length(insn)==2&&optimize<2)
+                       return \"jmpr cc_ULE,%l0\";
+                 else  
+                       return \"jmpa cc_ULE,%l0\";            
+                 }"
+     
+      [(set_attr "type" "branch")])
+
+
+
+
+
+(define_insn ""
+      [(set (pc)
+    	(if_then_else (eq (cc0)
+    			  (const_int 0))
+    		      (pc)
+    		      (label_ref (match_operand 0 "" ""))))
+      ]
+      ""
+      "*
+           {
+           if(get_attr_length(insn)==2&&optimize<2)
+                 return \"jmpr cc_NE,%l0\";
+           else  
+                 return \"jmpa cc_NE,%l0\";            
+           }"
+      [(set_attr "type" "branch")] )
+    
+    
+    
+    
+(define_insn ""
+      [(set (pc)
+    	(if_then_else (ne (cc0)
+    			  (const_int 0))
+    		      (pc)
+    		      (label_ref (match_operand 0 "" ""))))
+      ]
+      ""
+      "*
+           {
+           if(get_attr_length(insn)==2&&optimize<2)
+                 return \"jmpr cc_EQ,%l0\";
+           else  
+                 return \"jmpa cc_EQ,%l0\";            
+           }"
+      [(set_attr "type" "branch")] )
+    
+    
+    
+(define_insn ""
+      [(set (pc)
+    	(if_then_else (gt (cc0)
+    			  (const_int 0))
+    		      (pc)
+    		      (label_ref (match_operand 0 "" ""))))
+      ]
+      ""
+      "*
+           {
+           if(get_attr_length(insn)==2&&optimize<2)
+                 return \"jmpr cc_SLE,%l0\";
+           else  
+                 return \"jmpa cc_SLE,%l0\";            
+           }"
+      [(set_attr "type" "branch")] )
+    
+    
+    
+    
+(define_insn ""
+      [(set (pc)
+    	(if_then_else (gtu (cc0)
+    			   (const_int 0))
+    		      (pc)
+    		      (label_ref (match_operand 0 "" ""))))
+      ]
+      ""
+      "*
+           {
+           if(get_attr_length(insn)==2&&optimize<2)
+                 return \"jmpr cc_ULE,%l0\";
+           else  
+                 return \"jmpa cc_ULE,%l0\";            
+           }"
+      [(set_attr "type" "branch")] )
+    
+    
+    
+(define_insn ""
+      [(set (pc)
+    	(if_then_else (lt (cc0)
+    			  (const_int 0))
+    		      (pc)
+    		      (label_ref (match_operand 0 "" ""))))
+      ]
+      ""
+      "*
+           {
+           if(get_attr_length(insn)==2&&optimize<2)
+                 return \"jmpr cc_SGE,%l0\";
+           else  
+                 return \"jmpa cc_SGE,%l0\";            
+           }"
+      [(set_attr "type" "branch")] )
+    
+    
+    
+    
+(define_insn ""
+      [(set (pc)
+    	(if_then_else (ltu (cc0)
+    			   (const_int 0))
+    		      (pc)
+    		      (label_ref (match_operand 0 "" ""))))
+      ]
+      ""
+      "*
+           {
+           if(get_attr_length(insn)==2&&optimize<2)
+                 return \"jmpr cc_UGE,%l0\";
+           else  
+                 return \"jmpa cc_UGE,%l0\";            
+           }"
+      [(set_attr "type" "branch")] )
+    
+    
+    
+    
+(define_insn ""
+      [(set (pc)
+    	(if_then_else (ge (cc0)
+    			  (const_int 0))
+    		      (pc)
+    		      (label_ref (match_operand 0 "" ""))))
+      ]
+      ""
+      "*
+           {
+           if(get_attr_length(insn)==2&&optimize<2)
+                 return \"jmpr cc_SLT,%l0\";
+           else  
+                 return \"jmpa cc_SLT,%l0\";            
+           }"
+      [(set_attr "type" "branch")] )
+    
+    
+    
+(define_insn ""
+      [(set (pc)
+    	(if_then_else (geu (cc0)
+    			   (const_int 0))
+    		      (pc)
+    		      (label_ref (match_operand 0 "" ""))))
+      ]
+      ""
+      "*
+           {
+           if(get_attr_length(insn)==2&&optimize<2)
+                 return \"jmpr cc_ULT,%l0\";
+           else  
+                 return \"jmpa cc_ULT,%l0\";            
+           }"
+      [(set_attr "type" "branch")] )
+    
+    
+    
+(define_insn ""
+      [(set (pc)
+    	(if_then_else (le (cc0)
+    			  (const_int 0))
+    		      (pc)
+    		      (label_ref (match_operand 0 "" ""))))
+      ]
+      ""
+      "*
+           {
+           if(get_attr_length(insn)==2&&optimize<2)
+                 return \"jmpr cc_SGT,%l0\";
+           else  
+                 return \"jmpa cc_SGT,%l0\";            
+           }"
+      [(set_attr "type" "branch")] )
+    
+    
+    
+(define_insn ""
+      [(set (pc)
+    	(if_then_else (leu (cc0)
+    			   (const_int 0))
+    		      (pc)
+    		      (label_ref (match_operand 0 "" ""))))
+      ]
+      ""
+      "*
+           {
+           if(get_attr_length(insn)==2&&optimize<2)
+                 return \"jmpr cc_UGT,%l0\";
+           else 
+                 return \"jmpa cc_UGT,%l0\";            
+           }"
+      [(set_attr "type" "branch")] )
+
+    
+  
+  ;; Following RTL generates unconditional jump instruction
+  
+(define_insn "jump"
+    [(set (pc)
+    	(label_ref (match_operand 0 "" "")))
+      ]
+      ""
+  "*
+           {
+           if(get_attr_length(insn)==2&&optimize<2)
+                 return \"jmpr cc_UC,%l0\";
+           else 
+                 return \"jmpa cc_UC,%l0\";            
+           
+                 
+           }"
+      [(set_attr "type" "branch")]  )
+  
+  
+  ;;To generate indirect jump
+  
+(define_insn "indirect_jump"
+     [(set (pc) (match_operand 0 "general_operand" "rmn"))
+          (clobber (match_scratch:SI 1 "=&r"))
+    ]
+    ""
+    "mov %1,%0;\\n\\tjmpi cc_UC,[%1]"
+	[(set_attr "length" "8")] )
+
+
+   ;; RTL to match for nop instruction.
+   
+(define_insn "nop"
+     [(const_int 0)]
+      ""
+      "")
+      
+   ;;---------------------------------------------------------------------------------------------------------------------  
+     
+   ;;Following are the call instructions
+   ;;Call has two variants 
+   ;; 1.Call to a function which do not returns a value (Insn name used is call)
+   ;; 2.Call to a function which returns some value (Insn name used is call_value)
+   
+   
+(define_insn "call"
+     [(call (match_operand:HI 0 "general_operand" "or")
+   	 (match_operand:HI 1 "general_operand" "g"))]
+     ""
+     "* return output_call_insn1(operands);"
+     [(set (attr "length") (symbol_ref "compute_call_length (operands,0)"))]
+   )
+   
+   
+   
+   
+(define_expand "call_value"
+       [
+         (set (match_operand:HI 0 "" "=r")
+              (call (match_operand:HI 1 "general_call_operand" "ro")
+      	      (match_operand:HI 2 "general_operand" "g"))) 
+       ]
+       ""
+       "{
+         /* if(GET_CODE(operands[1])==MEM) */
+         if(GET_CODE(XEXP(operands[1],0))==PLUS)              
+         FAIL;
+   }" ) 
+ 
+ 
+ 
+ 
+(define_insn "*call_value"
+   [
+   (set (match_operand 0 "" "=r")
+        (call (match_operand:HI 1 "general_call_operand" "rR")
+	      (match_operand:HI 2 "general_operand" "g"))) 
+   ]
+  ""
+  "* return output_call_insn(operands);"
+  [(set (attr "length") (symbol_ref "compute_call_length (operands,1)"))]
+  )
+
+
+
+;;Following are the table jump insn formats for HI and PSI modes
+
+(define_expand "tablejump"
+  [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
+	      (use (label_ref (match_operand 1 "" "")))])]
+  ""
+  "")
+
+
+
+(define_insn "*tablejump"
+ [(set (pc) (match_operand:HI 0 "register_operand" "r"))
+   (use (label_ref (match_operand 1 "" "")))]
+  ""
+  "jmpi	cc_UC ,[%0]"
+)
+
+(define_insn "*tablejump_large"
+ [(set (pc) (match_operand:PSI 0 "register_operand" "r"))
+   (use (label_ref (match_operand 1 "" "")))]
+  ""
+  "jmpi	cc_UC ,[%0]"
+)
+;;*******************************************************************
+;;Following section contains all kind of compare instructions
+;;In Qi,Hi and Si mode
+
+;;Byte compare
+
+(define_insn "cmpqi"
+  [(set (cc0)
+	(compare (match_operand:QI 0 "register_operand" "b,b")
+		 (match_operand:QI 1 "nonmemory_operand" "b,n")))]
+  ""
+  "@
+  cmpb	%X0,%X1
+  cmpb  %X0,%X1"
+  [(set_attr "length" "2,4")]
+  )
+
+;;Compare operands in SI mode
+
+(define_insn "cmpsi"
+   [(set (cc0)
+ 	(compare (match_operand:SI 0 "register_operand" "r,r")
+ 		 (match_operand:SI 1 "nonmemory_operand" "r,n")))]
+   ""
+  "*
+  {
+  return output_cmppsi_insn(operands);
+  }
+  "
+  )
+
+;;compare operands in HI mode
+
+(define_insn "cmphi"
+  [(set (cc0)
+	(compare (match_operand:HI 0 "register_operand" "r,r,r")
+		 (match_operand:HI 1 "nonmemory_operand" "r,n,V")))]
+  ""
+  "*
+  {
+  if(which_alternative<2)
+  return \"cmp   %T0,%T1\";
+  else
+   {
+     if(TARGET_LARGE)
+      {
+       output_asm_insn(\"extp #PAG:%T1,#0x1\",operands);
+       return \"cmp %T0,POF:%T1\";
+      }
+     else
+  return \"cmp   %T0,%T1\";
+   }
+  }"
+ 
+ [(set_attr "length" "2,4,8")] 
+ )  
+	
+	
+;;----------------------------------------------------------------------------------------------------------------------	
+	
+	;;Peephole optimization 
+	;;Following peephole optimization is used basically for loops 
+	;;In this case it checks for consecutive add and compare instructions 
+	;;check register numbers in both the instructions and checks for intiger value in compare instruction
+	;;if appropriate conditions are matched then according to integer compare value
+	;;it emits one of (cmpd1,cmpd2,cmpi1,cmpi2) these instructions
+	
+;(define_peephole
+  
+;  [(set (match_operand:HI 0 "register_operand" "r")
+;        (plus:HI (match_operand:HI 1 "register_operand" "0")
+;        		 (match_operand:HI 2 "immediate_operand" "n")))
+;  
+;  (set (cc0)
+;	(compare (match_operand:HI 3 "register_operand" "r")
+;		 (match_operand:HI 4 "immediate_operand" "n")))]     		 
+  
+;  "REGNO(operands[0])==REGNO(operands[3])&&(INTVAL(operands[2])==-1||INTVAL(operands[2])==-2||INTVAL(operands[2])==1||INTVAL(operands[2])==2)"
+  
+;  {
+;  
+;       if(INTVAL(operands[2])==-1)
+;         return \"cmpd1 %0,%4\";
+;       else if (INTVAL(operands[2])==-2)
+;         return \"cmpd2 %0,%4\";
+;       else if (INTVAL(operands[2])==2)
+;                return \"cmpi2 %0,%4\";
+;       else if (INTVAL(operands[2])==1)
+;                return \"cmpi1 %0,%4\";
+;       
+;  }      
+;  
+;  ) 
+
+
+  ;;Following peephole optimization is used to generate bmovn instruction
+  ;;In the following case 
+  ;; cmpl Rwn
+  ;; mov Rwm,Rwl
+  ;; bmovn Rwn.i,Rwm.j are combined into
+  
+  ;; mov Rwn,Rwl
+  ;; bmovn Rwn.i,Rwm.j
+	
+   	
+(define_peephole
+   [(set (match_operand:QI 0 "register_operand" "=r")
+  	(not:QI (match_operand:QI 1 "register_operand" "0")))
+   
+    (set (match_operand:QI 2 "register_operand" "r")
+		(match_operand:QI 3 "register_operand" "r"))	
+
+    (set (zero_extract:HI (match_operand:HI 4 "register_operand" "")
+			 (match_operand:HI 5 "immediate_operand" "")
+			 (match_operand:HI 6 "general_operand" ""))
+	(match_operand:HI 7 "general_operand" ""))]
+	"REGNO(operands[0])==REGNO(operands[7])&&REGNO(operands[2])==REGNO(operands[4])"
+	{
+	 output_asm_insn(\"mov %2,%3\",operands);
+	 return \"bmovn %4.%s5,%7.0\";
+	}
+    )
+	
+	
+	
+	
+	
+	(define_insn "lshrpsi3"
+	    [(set (match_operand:PSI 0 "register_operand" "=r")
+	     (lshiftrt:PSI (match_operand:PSI 1 "register_operand" "0")
+	       		   (match_operand:PSI 2 "general_operand" "rn")))]
+	         "TARGET_LARGE"
+	         "* {
+	             if (GET_CODE (operands[2]) == CONST_INT 
+	                 && INTVAL (operands[2]) >= BITS_PER_WORD)
+	                  return (\"mov %0,#0     \");
+	             return (\"shr %0,%2\");
+	          }"
+           [(set_attr "length" "2")])
+	
+
+
+	
diff -Naur gcc-4.2-20060218orig/gcc/config/xc16x/xc16x-modes.def gcc-4.2-20060218/gcc/config/xc16x/xc16x-modes.def
--- gcc-4.2-20060218orig/gcc/config/xc16x/xc16x-modes.def	1970-01-01 05:30:00.000000000 +0530
+++ gcc-4.2-20060218/gcc/config/xc16x/xc16x-modes.def	2006-03-03 17:12:31.106602184 +0530
@@ -0,0 +1,18 @@
+/* This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+PARTIAL_INT_MODE (SI);
diff -Naur gcc-4.2-20060218orig/gcc/config/xc16x/xc16x.opt gcc-4.2-20060218/gcc/config/xc16x/xc16x.opt
--- gcc-4.2-20060218orig/gcc/config/xc16x/xc16x.opt	1970-01-01 05:30:00.000000000 +0530
+++ gcc-4.2-20060218/gcc/config/xc16x/xc16x.opt	2006-03-03 17:14:35.346714816 +0530
@@ -0,0 +1,40 @@
+; Options for the Infineon xc16x  port of the compiler
+;
+; Copyright (C) 2006 Free Software Foundation, Inc.
+;
+; This file is part of GCC.
+;
+; GCC is free software; you can redistribute it and/or modify it under
+; the terms of the GNU General Public License as published by the Free
+; Software Foundation; either version 2, or (at your option) any later
+; version.
+;
+; GCC is distributed in the hope that it will be useful, but WITHOUT
+; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+; License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with GCC; see the file COPYING.  If not, write to the Free
+; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
+; 02110-1301, USA.
+
+mtiny
+Target Mask(TINY)
+Generate tiny code
+
+msmall
+Target Mask(SMALL)
+Generate small code
+
+mlarge
+Target Mask(LARGE)
+Generate large code
+
+mintrom
+Target Mask(MINTROM)
+Put code in internal rom
+
+mnodppsave
+Target  Mask(NO_DPPSAVE)
+Don't save DPP for interrupt handlers
diff -Naur gcc-4.2-20060218orig/gcc/config/xc16x/xc16x-protos.h gcc-4.2-20060218/gcc/config/xc16x/xc16x-protos.h
--- gcc-4.2-20060218orig/gcc/config/xc16x/xc16x-protos.h	1970-01-01 05:30:00.000000000 +0530
+++ gcc-4.2-20060218/gcc/config/xc16x/xc16x-protos.h	2006-03-03 17:12:59.633265472 +0530
@@ -0,0 +1,43 @@
+/*Prototypes for xc16x.c functions used in the md file & elsewhere.
+   Copyright (C) 1 2006
+   Free Software Foundation, Inc.
+
+   Contributed by Shrirang Khisti On behalf of KPIT Cummins Infosystems ltd.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
+
+ GCC is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING.  If not, write to
+ the Free Software Foundation, 59 Temple Place - Suite 330,
+ Boston, MA 02111-1307, USA. */
+
+extern void print_operand (FILE *file, rtx x, int code);
+extern void print_operand_address (FILE *file, rtx x);
+const char * output_call_insn(rtx operands[3]);
+const char * output_call_insn1(rtx operands[3]);
+const char * op_or_insn(rtx *operands);
+const char * op_and_insn(rtx * operands);
+void xc16x_disable_intr(struct cpp_reader *);
+struct cpp_reader;
+extern void xc16x_interrupt_handler(struct cpp_reader *);
+extern void xc16x_interrupt_noreturn(struct cpp_reader *);
+const char * output_movpsi_insn(rtx *);
+const char * output_addpsi_insn(rtx ,rtx *,int flag);
+const char * output_cmppsi_insn(rtx *);
+const char * output_movhi_insn(rtx *);
+unsigned int compute_mov_length (rtx *operands);
+unsigned int compute_add_length (rtx *operands);
+unsigned int compute_call_length (rtx *operands,int number);
+const char * output_cmpsi_insn(rtx *);
+extern struct rtx_def *function_arg (int,
+				     enum machine_mode, tree, int);
diff -Naur gcc-4.2-20060218orig/gcc/config.gcc gcc-4.2-20060218/gcc/config.gcc
--- gcc-4.2-20060218orig/gcc/config.gcc	2006-02-18 16:42:51.000000000 +0530
+++ gcc-4.2-20060218/gcc/config.gcc	2006-03-03 17:10:50.413909800 +0530
@@ -2300,6 +2300,13 @@
 	extra_modes=arm/arm-modes.def
 	use_fixproto=yes
 	;;
+xc16x*-*-elf)tmake_file="xc16x/t-xc16x"
+             tm_define="TARGET_DEFAULT=(MASK_TINY)"
+        use_fixproto=yes
+        ;;
+xc16x-*)
+        ;;
+
 xscale-*-coff)
 	tm_file="arm/semi.h arm/aout.h arm/coff.h dbxcoff.h arm/xscale-coff.h arm/arm.h"
 	tmake_file="arm/t-arm arm/t-xscale-coff"
diff -Naur gcc-4.2-20060218orig/gcc/doc/contrib.texi gcc-4.2-20060218/gcc/doc/contrib.texi
--- gcc-4.2-20060218orig/gcc/doc/contrib.texi	2006-02-12 00:42:19.000000000 +0530
+++ gcc-4.2-20060218/gcc/doc/contrib.texi	2006-03-03 17:10:50.434906608 +0530
@@ -52,6 +52,10 @@
 Scott Bambrough for help porting the Java compiler.
 
 @item
+Shrirang Khisti at (KPITCummins Ltd.) for adding new target support for
+Infineon technologies  xc16x microcontroller series
+
+@item
 Wolfgang Bangerth for processing tons of bug reports.
 
 @item
diff -Naur gcc-4.2-20060218orig/gcc/doc/extend.texi gcc-4.2-20060218/gcc/doc/extend.texi
--- gcc-4.2-20060218orig/gcc/doc/extend.texi	2006-02-15 17:49:49.000000000 +0530
+++ gcc-4.2-20060218/gcc/doc/extend.texi	2006-03-03 17:10:50.495897336 +0530
@@ -1683,6 +1683,17 @@
 The @code{deprecated} attribute can also be used for variables and
 types (@pxref{Variable Attributes}, @pxref{Type Attributes}.)
 
+@item disable_intr
+@cindex @code{__attribute__ ((disable_intr))}
+This attribute is specific to xc16x Infineon
+processor. This attribute is used to disable all the interrupts during
+the function call
+
+@smallexample
+int fun() __attribute__ ((disable_intr));
+int fun()
+@end smallexample
+
 @item dllexport
 @cindex @code{__declspec(dllexport)}
 On Microsoft Windows targets and Symbian OS targets the
@@ -1930,7 +1941,7 @@
 The compiler will generate function entry and exit sequences suitable
 for use in an interrupt handler when this attribute is present.
 
-Note, interrupt handlers for the Blackfin, m68k, H8/300, H8/300H, H8S, and
+Note, interrupt handlers for the Blackfin, m68k, H8/300, H8/300H, H8S,xc16x  and
 SH processors can be specified via the @code{interrupt_handler} attribute.
 
 Note, on the AVR, interrupts will be enabled inside the function.
@@ -1946,11 +1957,15 @@
 
 @item interrupt_handler
 @cindex interrupt handler functions on the Blackfin, m68k, H8/300 and SH processors
-Use this attribute on the Blackfin, m68k, H8/300, H8/300H, H8S, and SH to
+Use this attribute on the Blackfin, m68k, H8/300, H8/300H, H8S, xc16x and SH to
 indicate that the specified function is an interrupt handler.  The compiler
 will generate function entry and exit sequences suitable for use in an
 interrupt handler when this attribute is present.
 
+@item interrupt_noreturn
+@cindex interrupt_noreturn for xc16x processor
+Use this attribute if interrupt handler function should not return to interrupted function
+
 @item kspisusp
 @cindex User stack pointer in interrupts on the Blackfin
 When used together with @code{interrupt_handler}, @code{exception_handler}
@@ -2327,6 +2342,16 @@
 This is useful, for example, when the function is referenced only in
 inline assembly.
 
+@item using_rbank
+@cindex @code{using_regno(rbank_no)} attribute
+This attribute is specific to Infineon xc16x processors. This attribute is
+used with the attribute interrupt_handler . Argument rbank_no  is used to
+ switchto the new register bank for interrupt handling.
+                                                                                                                                                                 
+@smallexample void fun() __attribute__ ((interrupt_handler,using_regno(0xfc20)));
+void fun()
+@end smallexample
+
 @item visibility ("@var{visibility_type}")
 @cindex @code{visibility} attribute
 The @code{visibility} attribute on ELF targets causes the declaration
diff -Naur gcc-4.2-20060218orig/gcc/doc/install.texi gcc-4.2-20060218/gcc/doc/install.texi
--- gcc-4.2-20060218orig/gcc/doc/install.texi	2006-01-31 17:26:46.000000000 +0530
+++ gcc-4.2-20060218/gcc/doc/install.texi	2006-03-03 17:10:50.505895816 +0530
@@ -2349,6 +2349,8 @@
 @item
 @uref{#x86-64-x-x,,x86_64-*-*, amd64-*-*}
 @item
+@uref{#xc16x-*-elf,,xc16x-*-elf}
+@item
 @uref{#xtensa-x-elf,,xtensa-*-elf}
 @item
 @uref{#xtensa-x-linux,,xtensa-*-linux*}
@@ -3926,6 +3928,14 @@
 @html
 <hr />
 @end html
+@heading @anchor{xc16x-*-elf}xc16x-*-elf
+Infineon xc16x Processor
+This configuration is intended for embedded systems.
+                                                                                
+@html
+<hr />
+@end html
+
 @heading @anchor{xtensa-x-elf}xtensa-*-elf
 
 This target is intended for embedded Xtensa systems using the
diff -Naur gcc-4.2-20060218orig/gcc/doc/invoke.texi gcc-4.2-20060218/gcc/doc/invoke.texi
--- gcc-4.2-20060218orig/gcc/doc/invoke.texi	2006-02-18 16:42:51.000000000 +0530
+++ gcc-4.2-20060218/gcc/doc/invoke.texi	2006-03-03 17:10:50.574885328 +0530
@@ -738,6 +738,9 @@
 @emph{x86-64 Options}
 See i386 and x86-64 Options.
 
+@emph{xc16x Options}
+@gccoptlist{-mtiny -mlarge -msmall -mno-dppsave }
+
 @emph{Xstormy16 Options}
 @gccoptlist{-msim}
 
@@ -7221,6 +7224,7 @@
 * V850 Options::
 * VAX Options::
 * x86-64 Options::
+* xc16x Options::
 * Xstormy16 Options::
 * Xtensa Options::
 * zSeries Options::
@@ -12731,6 +12735,34 @@
 
 These are listed under @xref{i386 and x86-64 Options}.
 
+@node xc16x Options
+@subsection xc16x Options
+@cindex xc16x Options
+                                                                                                                             
+@table @gcctabopt
+@item -mtiny
+@opindex mtiny
+Generate code for the tiny memory model of xc16x architecture.
+This is the default option set for compiling if no any other option is set .
+                                                                                                                             
+@item -mlarge
+@opindex mlarge
+Generate code for the large memory model of xc16x architecture.
+For this case code is generated using DPP overriding scheme
+                                                                                                                             
+@item -msmall
+@opindex msmall
+Generate code for the small memory model of xc16x architecture.
+                                                                                                                             
+@item -mno-dppsave
+@opindex mno-dppsave
+This option is used for interrupt handlers . Using this option Data page pointers  are not saved in
+the prologue of interrupt handler.
+@end table
+                                                                                                                             
+These @samp{-m} options are defined for the xc16x implementations:
+
+
 @node Xstormy16 Options
 @subsection Xstormy16 Options
 @cindex Xstormy16 Options
diff -Naur gcc-4.2-20060218orig/gcc/doc/md.texi gcc-4.2-20060218/gcc/doc/md.texi
--- gcc-4.2-20060218orig/gcc/doc/md.texi	2006-01-23 20:46:19.000000000 +0530
+++ gcc-4.2-20060218/gcc/doc/md.texi	2006-03-03 17:10:50.598881680 +0530
@@ -2840,6 +2840,22 @@
 
 @end table
 
+@item xc16x---@file{xc16x.h}
+@table @code
+@item b
+Eight bit register for QI mode operation
+                                                                                                                             
+@item S
+Memory operand having Symbol reference or Const
+                                                                                                                             
+@item T
+Memory operand having indirect register Plus displacement
+                                                                                                                             
+@item R
+Memory operand having indirect register or sybol reference
+                                                                                                                             
+@end table
+
 @item Xtensa---@file{xtensa.h}
 @table @code
 @item a
