How do I generate verilog with gnetlist? I have a simple schematic with a 7400 and a 7474, below.
I used gnetlist -g verilog -o test.vl test.sch. Gnetlist complains of pin numbers not being valid identifiers. I made symbols with pintype CHIPIN, CHIPOUT, etc., naming these 7400-vl.sym and 7474-vl.sym tomdean v 20060123 1 C 18900 54700 1 0 0 7400-vl.sym { T 19200 55600 5 10 1 1 0 0 1 refdes=U1 } C 22400 54300 1 0 0 7474-vl.sym { T 23700 56300 5 10 1 1 0 6 1 refdes=U2 } N 20200 55200 21400 55200 4 N 21400 55200 21400 55900 4 N 21400 55900 22400 55900 4 { T 21700 55900 5 10 1 1 0 0 1 netname=Q1 } N 22400 54900 22400 54400 4 N 22400 54400 18800 54400 4 { T 18800 54400 5 10 1 1 0 0 1 netname=CLK } N 18800 55000 18900 55000 4 { T 18800 55000 5 10 1 1 0 0 1 netname=B } N 18800 55400 18900 55400 4 { T 19000 54700 5 10 1 1 0 0 1 netname=A T 18800 55400 5 10 1 1 0 0 1 netname=A } N 24000 55900 24200 55900 4 { T 24100 55900 5 10 1 1 0 0 1 netname=Q } N 24000 54900 24200 54900 4 { T 24200 54900 5 10 1 1 0 0 1 netname=NOTQ } N 23200 56500 23200 56600 4 N 23200 56600 18800 56600 4 { T 18900 56600 5 10 1 1 0 0 1 netname=CLR } N 23200 54300 23200 54000 4 N 23200 54000 18800 54000 4 { T 18900 54000 5 10 1 1 0 0 1 netname=PRE } _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user