ldoolitt-dhTElhTvxjT/[EMAIL PROTECTED] wrote: > I have added some odd features > over the past couple of years. Like the ability to automatically > create a .ucf file with timing goals in it based on the comments > in the top level Verilog module: > > module stacker( > input clk, // timespec 6.5 ns > input gate, > ... > > which is useful for keeping track of timing and cell usage for > each of the components of a design.
I use attributes for this sort of thing: module stacker( (* PERIOD="6.5ns" *) input clk, ... xst understands this, as does Icarus Verilog. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user