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my real problem has to do with the fact that my FET's package is SO8. 3 pins are source, 4 are drain and 1 is gate. How to I convey to gschem that the single source and drain symbol pins should actually be connected to multiple physical pins?
Redraw the symbol to incorporate multiple pins. Name them s1, s2, s3, d1, d2, d3, d4, and g. Then draw your PCB footprint to match the symbol. By the way, this is what you do in ViewDraw, Orcad, or any other commerical package. Stuart _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
