Andy Peters schrieb:
It might be easier to work backwards, from the schematic, and have it back-annotate into the .ucf (user constraint file), which is the file used by the Xilinx tools for pinouts (and timing specs, etc etc).
It's true that ripping off everything exept the pairing Pin Names <-> Pin Numbers from the gschem symbol is a snap compared to building/ updating a symbol from the Fitter report. But how would you make sure that the user of gschem doesn't put an input pin at an reserved location, i.e. a JTAG or PWR pin. The timing issues following from forcing the Xilinx tool to use a user-defined pin-out are non-trivial IMHO, at least for CPLDs. So I guess it would be better regarding timing issues to run Xilinx ISE (or another vendor's tool) first and then go to gschem and create/update the symbol.
But nevertheless, I'm looking forward to the new FPGA flow ... The (at the moment) missing link between logic design tools and gschem is a big show-stopper for the gEDA suite, I guess. - cl _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user