Your example below is within the skills of Icarus Verilog, but there was a very recent fix for exactly this problem. According to my git logs, it was committed 6/11/2007, which is *after* the very last snapshot. So try the current git. (It should be in the present but stopped CVS as well.)
Matt Ettus wrote: > I have the following code in a module: > > genvar i; > > generate > for (i=0;i<32;i=i+1) > begin : gen_srl16 > SRL16E > srl16e(.Q(dataout[i]), > .A0(a[0]),.A1(a[1]),.A2(a[2]),.A3(a[3]), > .CE(write),.CLK(clk),.D(datain[i])); > end > endgenerate > > > Icarus gives me the following compilation error: > > shortfifo.v:18: error: Index of dataout needs to be constant in this context. > shortfifo.v:18: : Index expression is: i > shortfifo.v:18: error: Output port expression must support continuous > assignment. > shortfifo.v:18: : Port of SRL16E is Q -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user