Timothy Normand Miller wrote: > Sorry about the cross-post. We're -><- THIS close to getting OGD1 > done, with artwork in the hands of board makers who are working on > quotes, and we've discovered a problem that could make the video > output unacceptable. > > We've discovered that the clock generators in the Xilinx FPGA part are > lousy for generating video clocks. We're seeing like 900ps of jitter, > which causes artifacts on DVI monitors at resolutions as low as > 1280x1024 when the cable gets beyond a certain length. (I don't > recall all the details.) > > One option is to use the clock generators in the Lattice part, but > even they have like 400ps of jitter, and they also severely limit the > range of frequencies we can generate. > > So the best solution we can come up with is to put on some external > clock generators. One for each video head. Problems: (1) more time > to mod the design, (2) up to $15 each for the generators, (3) we have > no idea what generators to use, how good they are, how to wire them. > > Does anyone know anything about these? Do you have experience with > specific high-frequency clock generators and know how they perform and > what kind of jitter they produce?
Try the MAX3674. Jitter is less than a picosecond or two. Stick a crystal one side and you can program the thing for and output from 21.25MHz to 1360MHz. It has parallel or I2C programming. PSRR is good. http://www.maxim-ic.com/quick_view2.cfm/qv_pk/5634 -Dan _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user