On Jan 21, 2008, at 11:59 AM, a r wrote: > On Jan 21, 2008 6:02 PM, John Doty <[EMAIL PROTECTED]> wrote: >> >> On Jan 21, 2008, at 10:43 AM, John Griessen wrote: >> >>> John Doty wrote: >>> >>>>> - clean schematics are needed for LVS, >>>> >>>> What's LVS? Please don't assume we know your jargon. >>>> >>> Layout Versus Schematic checker. EDA jargon. Chip design jargon. >>> Our jargon. >>> >> >> The people I work with call it "postlayout verification", and the >> schematic isn't directly involved: we do it at the netlist level. I >> don't see how you'd do it at the schematic level: the extracted >> netlists from the layout correspond to schematics that are humanly >> incomprehensible! But again, I am very far from the VLSI >> "mainstream". > > That's a bit off-topic but it's better if I explain this topic a bit.
Understanding what other people's flows are like is important for the future evolution of gEDA. Do not assume that everybody's flows are like your own. > > LVS is a method of comparing layout vs. schematics. It starts with two > netlists - one obtained from schematics (usually a spice-like .cdl > format, verilog gate-level netlists for logic), the other extracted > from layout (without parasitics). OK, the layout contractor may be doing that, but with distance, language barrier and the fact that I deal with them indirectly through Osaka U., I have little insight into their internal flow. What they get from me is PDF schematics and other documentation along with stripped-down SPICE netlists (just the circuits, no models or simulation commands). That seems to suit them, and gEDA is a very effective tool for generating this. > In fact, you can compare netlists > obtained from two schematics (sometimes it's called SVS) or two layout > (this is rarely used - layouts are usually compared geometrically). > It's basically a tool, which says that the layout you have drawn is > same as schematics you have started from (in terms of primitive > devices used and their interconnections). It seems like netlists, not schematics, are the basis here. I don't see why that is at all a problem for gEDA as currently structured. Either a separate tool or a gnetlist back end could do this. I don't see why you think a spice-subcircuit-LL component could get in the way here. > > LVS is one of _layout_ verification methods. Others are DRC (often > separated into several checks: antenna, density etc), ERC, LVL (GDS > compare). I don't know what open source tools exist here. It would be interesting to investigate incorporating them into a gEDA flow. > > Post-layout verification refers usually to the extracted circuit > simulations. Yes. And to me that's the most important: will the cells *behave* as expected? Will the chip work? gEDA's not bad here: just substitute the extracted netlists for the schematic derived ones and simulate until the submission deadline forces you to declare the job done ;-) John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ [EMAIL PROTECTED] _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user