Hi John, >> John Wrote: >> Is your ultimate target HW/SW design a PC connected to the parallel port of another custom system board, >> and thus a fairly low speed, (parallel port speed), design? >> Is the convenient simulation done with actual software and a >> iverilog simulation without going through the parallel port?
Yes, John that what I think about, also I think about boards connect through other others interfaces e.g. serial ports, USB >> I'm not seeing "speedy circuit" value yet for lack of understanding... >> Is the value in code testing at lower than normal operating speed? Sorry John, I did not get your point here, I think you mean that the emulator expects to work on the normal operating speed of e.g. parallel port and the simulator will work on the simulation speed, which means 1ms in simulator clock may map to 1 second - depending on the performance if simulator and the complexity of the simulated circuit - in the real life clock which is the same as emulator clock. >> Steve Said: >> I think this is an excellent idea, but a bigger one then you >> might realize. I hope that it will not be that huge :), that is why I open this discussion with you. >> For example, for a PCI device, the HDL writer will need the test >> environment to create PCI cycles (including the clocks) at a *far* >> lower level then qemu, for example, provides. Emulating at the BUS >> cycle level would drastically slow down a PC emulator. PCI device simulation i think about but with some respect, but i did not have a well understanding to it yet, i have some theoretical background about it, i think Larry will help us, how he handles this in his project, but sorry if my question seems to be a bit silly and not practical , could I do the simulation at byte level or even at bit level. some thing like sending values to the PCI device and wait for response as bytes or bits? >> For USB devices or firewire devices, you might be able make up a >> hookup point where you can tunnel from the emulator over to a >> simulation process. Good news at last :), as i mentioned earlier i already have a prototype with qemu and jHDL, I use named pipes to tunnels the data by modifying the parallel.c code in the qemu, but i could use better approach if i start it for real. >> Note that for this to work, you are going to need to know a lot >> about the particular interface you are simulating, because the >> emulators themselves know nothing. I hope it will be useful knowledge ;). Best regards, asayed
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