High speed memory is now staggering the transmission of each data line to minimize cross talk. High end fpga's can support qdr II memory devices to clock speeds of over 500 MHz. The qdr ii has two data buses one for read and one for writing. Each bus supports a transfer on each edge of the clock. This implies data rates on these buses of over 1 GHz.
It isn't the bus rate that will limit performance it is the internal clock rate. 500 MHz as opposed to over 3 GHZ. However, the fpga has all those built in multipliers.... hundreds of them. So for certain tasks an fpga will completely blow away a standard intel based computer. My inclination would be to build a mother board with both a standard microprocessor and an additional fpga that can be programed by the microprocessor. A customized coprocessor so to speak. Steve Meier On Thu, 2008-03-27 at 19:08 -0400, DJ Delorie wrote: > > My understanding is that with the GHz busses on modern mobos you need > > With a soft CPU, the busses can go slower. I wouldn't expect such a > project to compete with PCs. > > > I thought it was basically impossible to get it right without > > assistance from the CAD tool. > > Well, we can change the CAD tool, can't we? ;-) > > > Is this actually practically feasible with a "dumb" CAD tool like > > pcb? > > You'd have to limit yourself to something that fits in our skill set, > sure, but perhaps a less-than-GHz system would be doable. It would be > neat to experiment with other cores and stuff besides the usual x86, > arm, and mips. Imagine a picoblaze PC running something like DOS, or > a nios-linux box. > > > But it's "dumb" in the sense that it doesn't really contribute to > > the layout, > > It does have trace measuring, though. > > > _______________________________________________ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user