Does anybody have access to a Verilog-AMS tool and can said person attempt to run the attached sample program? It is a very simple program, but it is an attempt to test some of my understanding of very basic principles of Verilog-AMS.
I understand that Verilog-AMS tools are very few and very far between, but I would like to work on that problem. This example, though trivial in the extreme, covers a fair amount. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."
`include "disciplines.vams" // Module provides at the output the absolute value of the input voltage module V_absolute(in,out); input in; output out; voltage in,out; analog V(out) <+ abs(V(in)); endmodule module main; real value; voltage drv, res; analog V(drv) <+ value; V_absolute U (drv, res); initial begin value = 1.0; #1 if (V(res) != abs(value)) begin $display("FAILED -- value=%g, res=%g", value, V(res)); $finish; end value = -1.0; #1 if (V(res) != abs(value)) begin $display("FAILED -- value=%g, res=%f", value, V(res)); $finish; end $display("PASSED"); end endmodule // main
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