On Tue, 2008-11-11 at 13:13 +0000, Simon Clubley wrote: > On 08/11/2008, Simon Clubley <[EMAIL PROTECTED]> wrote:
> In order to make selecting the individual track segments easier, I > also switched to Power sized tracks, and Signal sized vias. I get lots > of DRC warnings, but the example circuit from the tutorial routed just > fine when laid out on this veroboard layout. Perhaps you could post that as an example, or make some screen-shots available on the web somewhere? I'm curious to see what this looks like. Regards, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user