> What you want to do is make mcu_cson mcu_wron etc registers. hmmmm...
Those values are clock counts programmed into the MCU's bus control registers. There's a different count for turning the signal on vs turning it off, and the counts depend on the address as well. I'm modelling a chip select-style addr/data bus, so the timing parameters depend on which memory area is being addressed. This is in the testbench, not the FPGA code. Here's a bigger chunk of code. BCLK is the bus clock; all things happen on a rising edge, and bclk1 and bclk2 are tasks that wait for the two edges to happen. twait() is supposed to wait for the right number of bclk edges. initial begin cson[1] = 0; csrwait[1] = 6; rdon[1] = 2; csroff[1] = 1; wdon[1] = 0; wron[1] = 0; cswwait[1] = 6; wdoff[1] = 1; cswoff[1] = 1; cson[3] = 0; rdon[3] = 1; csrwait[3] = 2; csroff[3] = 1; wdon[3] = 0; wron[3] = 0; cswwait[3] = 0; wdoff[3] = 1; cswoff[3] = 1; cson[4] = 0; rdon[4] = 1; csrwait[4] = 2; csroff[4] = 1; wdon[4] = 0; wron[4] = 0; cswwait[4] = 0; wdoff[4] = 1; cswoff[4] = 1; end reg mcu_cson_running = 0; task mcu_cson; input [23:0] address; begin mcu_cson_running = 1; twait(cson[cs]); case (address[23:20]) 3: cs3 = 0; 4: cs4 = 0; endcase mcu_cson_running = 0; end endtask reg mcu_cswoff_running = 0; task mcu_cswoff; input [23:0] address; begin mcu_cswoff_running = 1; twait(cswoff[cs]); cs3 = 1; cs4 = 1; mcu_cswoff_running = 0; end endtask task mcu_write; input [23:0] address; input [15:0] data; input [1:0] bhl; begin cs = address[23:20]; bclk1; a = address; d_val = data; rd = 1; mcu_state = 1; fork mcu_cson (address); mcu_wron (address); mcu_wdon (address); mcu_cswwait (address); join mcu_state = 2; bclk0; bclk1; wr0 = 1; wr1 = 1; mcu_state = 3; fork mcu_wdoff (address); mcu_cswoff (address); join mcu_state = 4; end endtask _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user