al davis wrote:
>> Graphics information would be lost during the process.
> Yes .. you missed something. Verilog has a structural part too,
> which is well documented, has a published standard, and
> completely adequate for this.
Hmm, "structural" in the context of verilog always seemed to mean
"description by gates" rather than "description by behavior". That
is, you are still stuck with expressions like
(a NAND NOT b) AND (b OR c)
But no geometry information on where to put the gates in a schematic
representation.
Maybe we just misunderstand each other.
---<)kaimartin(>---
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