On Thu, 10 Mar 2011 13:34:17 +0000 Thomas Oldbury <toldb...@gmail.com> wrote:
> I am using an outline layer in PCB. It complains of DRC violations > when the outline is too close to vias. Is it possible to get it to > skip DRC on these? I theory, yes. You should apply the patch found in my last message. See the instructions found in here. http://www.seul.org/pipermail/geda-user/2010-September/048721.html However, it is not a good idea to place vias close to the edge of the board. Levente -- Kovacs Levente <leventel...@gmail.com> Voice: +36705071002 _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
