On Thu, Mar 10, 2011 at 7:34 AM, Thomas Oldbury <toldb...@gmail.com> wrote: > I am using an outline layer in PCB. It complains of DRC violations when > the outline is too close to vias. Is it possible to get it to skip DRC > on these? > >
Previous discussion: http://archives.seul.org/geda/user/Feb-2010/msg00209.html -- Mark Rages, Engineer Midwest Telecine LLC markra...@midwesttelecine.com _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
