----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2340/ -----------------------------------------------------------
(Updated Aug. 15, 2014, 2:24 p.m.) Review request for Default. Repository: gem5 Description (updated) ------- Changeset 10307:c8deb72db38a --------------------------- cpu, mem: Make software prefetches non-blocking Previously, they were treated so much like loads that they could stall at the head of the ROB. Now they are always treated like L1 hits. If they actually miss, a new request is created at the L1 and tracked from the MSHRs there if necessary (i.e. if it didn't coalesce with an existing outstanding load). Diffs (updated) ----- src/mem/cache/blk.hh 79fde1c67ed8 src/mem/cache/cache.hh 79fde1c67ed8 src/mem/cache/cache_impl.hh 79fde1c67ed8 src/mem/packet.hh 79fde1c67ed8 Diff: http://reviews.gem5.org/r/2340/diff/ Testing ------- Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
