Dear sir or madam,
We were trying to use M5 to build a memory scheduler to change the order of
the memory requests. I want to know the architecture of M5 memory controller. I
can't find any memory request queue(MRQ) in dram.cc, which only calculates the
memory request delay. I tried to add a memory request queue and a out-of-order
scheduler, but I can't find the port between bus and dram, the control signal
between L2 cache and dram(dram busy signal and so on). Can you help me.
Sincerely,
Tian Hangpei
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