=== modified file 'boot/arch/arm32/src/asm.S'
--- boot/arch/arm32/src/asm.S	2013-08-15 09:36:14 +0000
+++ boot/arch/arm32/src/asm.S	2013-09-28 20:05:38 +0000
@@ -68,7 +68,7 @@
 #define CP15_C1_DC		2
 
 
-#ifndef PROCESSOR_ARCH_armv7_a
+#if !defined PROCESSOR_ARCH_armv7_a && !defined PROCESSOR_ARCH_armv6
 	mrc	p15, 0, r4, c1, c0, 0
 	
 	# D-cache before the kernel is started.

=== modified file 'boot/arch/arm32/src/mm.c'
--- boot/arch/arm32/src/mm.c	2013-08-25 23:39:59 +0000
+++ boot/arch/arm32/src/mm.c	2013-09-28 20:05:55 +0000
@@ -139,7 +139,7 @@
 	pte->domain = 0;
 	pte->should_be_zero_1 = 0;
 	pte->access_permission_0 = PTE_AP_USER_NO_KERNEL_RW;
-#ifdef PROCESSOR_ARCH_armv7_a
+#if defined PROCESSOR_ARCH_armv7_a || defined PROCESSOR_ARCH_armv6
 	/*
 	 * Keeps this setting in sync with memory type attributes in:
 	 * init_boot_pt (boot/arch/arm32/src/mm.c)

=== modified file 'kernel/arch/arm32/include/arch/mm/page_armv6.h'
--- kernel/arch/arm32/include/arch/mm/page_armv6.h	2013-08-08 20:59:02 +0000
+++ kernel/arch/arm32/include/arch/mm/page_armv6.h	2013-09-28 20:01:30 +0000
@@ -257,7 +257,7 @@
 
 	if (flags & PAGE_CACHEABLE) {
 		/*
-		 * Write-through, no write-allocate memory, see ch. B3.8.2
+		 * Write-through, write-allocate memory, see ch. B3.8.2
 		 * (p. B3-1358) of ARM Architecture reference manual.
 		 * Make sure the memory type is correct, and in sync with:
 		 * init_boot_pt (boot/arch/arm32/src/mm.c)