From: Ville Syrjälä <ville.syrj...@linux.intel.com>
intel_crtc_compute_config() and i9xx_set_pipeconf() attempt to get
the current pixel clock from requested_mode. requested_mode.clock may
be totally bogus, so the clock should come from adjusted_mode.
Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index ecb8b52..cab1319 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4124,8 +4124,7 @@ static int intel_crtc_compute_config(struct intel_crtc
*crtc,
if (HAS_PCH_SPLIT(dev)) {
/* FDI link clock is fixed at 2.7G */
- if (pipe_config->requested_mode.clock * 3
- > IRONLAKE_FDI_FREQ * 4)
+ if (adjusted_mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
return -EINVAL;
}
@@ -4812,7 +4811,7 @@ static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc)
* XXX: No double-wide on 915GM pipe B. Is that the only reason
for the
* pipe == 0 check?
*/
- if (intel_crtc->config.requested_mode.clock >
+ if (intel_crtc->config.adjusted_mode.clock >
dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
pipeconf |= PIPECONF_DOUBLE_WIDE;
}
--
1.8.1.5
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